| #************************************************************** |
| # Create Clock |
| #************************************************************** |
| |
| derive_pll_clocks |
| |
| # JTAG Signal Constraints constrain the TCK port, assuming a 10MHz JTAG clock and 3ns delays |
| create_clock -name {altera_reserved_tck} -period 41.667 [get_ports { altera_reserved_tck }] |
| set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tdi] |
| set_input_delay -clock altera_reserved_tck -clock_fall -max 5 [get_ports altera_reserved_tms] |
| set_output_delay -clock altera_reserved_tck 5 [get_ports altera_reserved_tdo] |
| |
| create_clock -name {CLK_50} -period 20.000 {clk_50} |
| |
| set_false_path -to [get_ports {user_led[*]}] |
| set_false_path -to [get_ports {fpga_reset_n}] |
| set_false_path -from [get_ports {fpga_reset_n}] |
| |
| # UART |
| set_false_path -from * -to [get_ports {uart_tx}] |
