| /* Copyright (c) 2025 Texas Instruments Incorporated |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #ifndef ZEPHYR_DRIVERS_TIMERS_TI_RTI_TIMER_H_ |
| #define ZEPHYR_DRIVERS_TIMERS_TI_RTI_TIMER_H_ |
| |
| #include <zephyr/devicetree.h> |
| |
| /* |
| * Refer to "AM261x Sitara Microcontrollers Technical Reference Manual" (Rev. B) (revised May 2025) |
| * from Texas Instruments for more information on this peripheral. |
| * |
| * Registers are documented in a separate Register Addendum document, |
| * "AM261x Sitara Microcontrollers Register Addendum" (Rev. A) (revised April 2025) |
| */ |
| |
| /************************************************************************** |
| * Register Macros |
| **************************************************************************/ |
| |
| #define TI_RTI_TIMER_RTIGCTRL (0x00000000U) |
| #define TI_RTI_TIMER_RTITBCTRL (0x00000004U) |
| #define TI_RTI_TIMER_RTICAPCTRL (0x00000008U) |
| #define TI_RTI_TIMER_RTICOMPCTRL (0x0000000CU) |
| #define TI_RTI_TIMER_RTIFRC0 (0x00000010U) |
| #define TI_RTI_TIMER_RTIUC0 (0x00000014U) |
| #define TI_RTI_TIMER_RTICPUC0 (0x00000018U) |
| #define TI_RTI_TIMER_RTICAFRC0 (0x00000020U) |
| #define TI_RTI_TIMER_RTICAUC0 (0x00000024U) |
| #define TI_RTI_TIMER_RTIFRC1 (0x00000030U) |
| #define TI_RTI_TIMER_RTIUC1 (0x00000034U) |
| #define TI_RTI_TIMER_RTICPUC1 (0x00000038U) |
| #define TI_RTI_TIMER_RTICAFRC1 (0x00000040U) |
| #define TI_RTI_TIMER_RTICAUC1 (0x00000044U) |
| #define TI_RTI_TIMER_RTICOMP0 (0x00000050U) |
| #define TI_RTI_TIMER_RTIUDCP0 (0x00000054U) |
| #define TI_RTI_TIMER_RTICOMP1 (0x00000058U) |
| #define TI_RTI_TIMER_RTIUDCP1 (0x0000005CU) |
| #define TI_RTI_TIMER_RTICOMP2 (0x00000060U) |
| #define TI_RTI_TIMER_RTIUDCP2 (0x00000064U) |
| #define TI_RTI_TIMER_RTICOMP3 (0x00000068U) |
| #define TI_RTI_TIMER_RTIUDCP3 (0x0000006CU) |
| #define TI_RTI_TIMER_RTITBLCOMP (0x00000070U) |
| #define TI_RTI_TIMER_RTITBHCOMP (0x00000074U) |
| #define TI_RTI_TIMER_RTISETINT (0x00000080U) |
| #define TI_RTI_TIMER_RTICLEARINT (0x00000084U) |
| #define TI_RTI_TIMER_RTIINTFLAG (0x00000088U) |
| #define TI_RTI_TIMER_RTIDWDCTRL (0x00000090U) |
| #define TI_RTI_TIMER_RTIDWDPRLD (0x00000094U) |
| #define TI_RTI_TIMER_RTIWDSTATUS (0x00000098U) |
| #define TI_RTI_TIMER_RTIWDKEY (0x0000009CU) |
| #define TI_RTI_TIMER_RTIDWDCNTR (0x000000A0U) |
| #define TI_RTI_TIMER_RTIWWDRXNCTRL (0x000000A4U) |
| #define TI_RTI_TIMER_RTIWWDSIZECTRL (0x000000A8U) |
| #define TI_RTI_TIMER_RTIINTCLRENABLE (0x000000ACU) |
| #define TI_RTI_TIMER_RTICOMP0CLR (0x000000B0U) |
| #define TI_RTI_TIMER_RTICOMP1CLR (0x000000B4U) |
| #define TI_RTI_TIMER_RTICOMP2CLR (0x000000B8U) |
| #define TI_RTI_TIMER_RTICOMP3CLR (0x000000BCU) |
| |
| /************************************************************************** |
| * Field Definition Macros |
| **************************************************************************/ |
| |
| /* RTIGCTRL */ |
| |
| #define TI_RTI_TIMER_RTIGCTRL_CNT0EN_MASK (0x00000001U) |
| #define TI_RTI_TIMER_RTIGCTRL_CNT0EN_SHIFT (0x00000000U) |
| |
| #define TI_RTI_TIMER_RTIGCTRL_COS_MASK (0x00008000U) |
| #define TI_RTI_TIMER_RTIGCTRL_COS_SHIFT (0x0000000FU) |
| |
| /* RTITBCTRL */ |
| |
| #define TI_RTI_TIMER_RTITBCTRL_TBEXT_MASK (0x00000001U) |
| #define TI_RTI_TIMER_RTITBCTRL_TBEXT_SHIFT (0x00000000U) |
| |
| /* RTICAPCTRL */ |
| |
| #define TI_RTI_TIMER_RTICAPCTRL_CAPCNTR0_MASK (0x00000001U) |
| #define TI_RTI_TIMER_RTICAPCTRL_CAPCNTR0_SHIFT (0x00000000U) |
| |
| /* RTICOMPCTRL */ |
| |
| #define TI_RTI_TIMER_RTICOMPCTRL_COMP0SEL_MASK (0x00000001U) |
| #define TI_RTI_TIMER_RTICOMPCTRL_COMP0SEL_SHIFT (0x00000000U) |
| |
| /* RTIFRC0 */ |
| |
| #define TI_RTI_TIMER_RTIFRC0_FRC0_MASK (0xFFFFFFFFU) |
| #define TI_RTI_TIMER_RTIFRC0_FRC0_SHIFT (0x00000000U) |
| |
| /* RTIUC0 */ |
| |
| #define TI_RTI_TIMER_RTIUC0_UC0_MASK (0xFFFFFFFFU) |
| #define TI_RTI_TIMER_RTIUC0_UC0_SHIFT (0x00000000U) |
| |
| /* RTICPUC0 */ |
| |
| #define TI_RTI_TIMER_RTICPUC0_CPUC0_MASK (0xFFFFFFFFU) |
| #define TI_RTI_TIMER_RTICPUC0_CPUC0_SHIFT (0x00000000U) |
| |
| /* RTICOMP0 */ |
| |
| #define TI_RTI_TIMER_RTICOMP0_COMP0_MASK (0xFFFFFFFFU) |
| #define TI_RTI_TIMER_RTICOMP0_COMP0_SHIFT (0x00000000U) |
| |
| /* RTIUDCP0 */ |
| |
| #define TI_RTI_TIMER_RTIUDCP0_UDCP0_MASK (0xFFFFFFFFU) |
| #define TI_RTI_TIMER_RTIUDCP0_UDCP0_SHIFT (0x00000000U) |
| |
| /* RTISETINT */ |
| |
| #define TI_RTI_TIMER_RTISETINT_SETINT0_MASK (0x00000001U) |
| #define TI_RTI_TIMER_RTISETINT_SETINT0_SHIFT (0x00000000U) |
| |
| /* RTICLEARINT */ |
| |
| #define TI_RTI_TIMER_RTICLEARINT_CLEARINT0_MASK (0x00000001U) |
| #define TI_RTI_TIMER_RTICLEARINT_CLEARINT0_SHIFT (0x00000000U) |
| |
| /* RTIINTFLAG */ |
| |
| #define TI_RTI_TIMER_RTIINTFLAG_INT0_MASK (0x00000001U) |
| #define TI_RTI_TIMER_RTIINTFLAG_INT0_SHIFT (0x00000000U) |
| |
| #define TI_RTI_TIMER_RTIINTFLAG_OVL0INT_MASK (0x00020000U) |
| #define TI_RTI_TIMER_RTIINTFLAG_OVL0INT_SHIFT (0x00000011U) |
| |
| #endif /* ZEPHYR_DRIVERS_TIMERS_TI_RTI_TIMER_H_ */ |
