| # STM32 LTDC display driver configuration options |
| |
| # Copyright (c) 2022 Byte-Lab d.o.o. <dev@byte-lab.com> |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| menuconfig STM32_LTDC |
| bool "STM32 LCD-TFT display controller driver" |
| default y |
| depends on DT_HAS_ST_STM32_LTDC_ENABLED |
| select USE_STM32_HAL_LTDC |
| select USE_STM32_HAL_RIF if SOC_SERIES_STM32N6X |
| select CACHE_MANAGEMENT if CPU_HAS_DCACHE |
| select PINCTRL |
| help |
| Enable driver for STM32 LCT-TFT display controller periheral. |
| |
| if STM32_LTDC |
| |
| choice STM32_LTDC_PIXEL_FORMAT |
| prompt "Color pixel format" |
| default STM32_LTDC_RGB565 |
| depends on STM32_LTDC |
| help |
| Specify the color pixel format for the STM32 LCD-TFT display controller. |
| |
| config STM32_LTDC_ARGB8888 |
| bool "ARGB8888" |
| help |
| One pixel consists of 8-bit alpha, 8-bit red, 8-bit green and 8-bit blue value |
| (4 bytes per pixel) |
| |
| config STM32_LTDC_RGB888 |
| bool "RGB888" |
| help |
| One pixel consists of 8-bit red, 8-bit green and 8-bit blue value |
| (3 bytes per pixel) |
| |
| config STM32_LTDC_RGB565 |
| bool "RGB565" |
| help |
| One pixel consists of 5-bit red, 6-bit green and 5-bit blue value |
| (2 bytes per pixel) |
| |
| endchoice |
| |
| config STM32_LTDC_FB_NUM |
| int "Frame buffer number" |
| default 1 |
| range 0 2 |
| help |
| STM32 LTDC frame buffer number config: |
| - 0 frame buffer maintained by application, must write with full screen pixels. |
| - 1 single frame buffer in stm32 ltdc driver. |
| - 2 double frame buffer in stm32 ltdc driver. |
| |
| config STM32_LTDC_FB_USE_SHARED_MULTI_HEAP |
| bool "Use shared multi heap for the display buffer" |
| |
| config STM32_LTDC_FB_SMH_ATTRIBUTE |
| int "Shared multi heap attribute for the display buffer" |
| depends on STM32_LTDC_FB_USE_SHARED_MULTI_HEAP |
| default 0 |
| range 0 2 |
| help |
| Shared multi heap attribute for the display buffer: |
| 0: SMH_REG_ATTR_CACHEABLE |
| 1: SMH_REG_ATTR_NON_CACHEABLE |
| 2: SMH_REG_ATTR_EXTERNAL |
| |
| config STM32_LTDC_DISABLE_FMC_BANK1 |
| bool "Disable FMC bank1 for STM32F7/H7 series" |
| depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32F7X |
| default y |
| help |
| Disable FMC bank1 if not used to prevent speculative read accesses. |
| Refer to AN4861 "4.6 Special recommendations for Cortex-M7 (STM32F7/H7)". |
| |
| endif # STM32_LTDC |
