blob: 879a72533ec3b5c93eb8bd36f7a1459b4c982f35 [file] [log] [blame]
/*
* Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com>
* Copyright (c) 2022 Georgij Cernysiov <geo.cgv@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/h7/stm32h7.dtsi>
#include <zephyr/dt-bindings/display/stm32_ltdc.h>
#include <zephyr/dt-bindings/flash_controller/ospi.h>
/ {
soc {
flash-controller@52002000 {
flash0: flash@8000000 {
compatible = "st,stm32-nv-flash", "soc-nv-flash";
write-block-size = <32>;
erase-block-size = <DT_SIZE_K(128)>;
/* maximum erase time for a 128K sector */
max-erase-time = <4000>;
};
};
uart9: serial@40011800 {
compatible = "st,stm32-uart";
reg = <0x40011800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
interrupts = <155 0>;
status = "disabled";
};
usart10: serial@40011c00 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
interrupts = <156 0>;
status = "disabled";
};
dmamux1: dmamux@40020800 {
dma-requests= <129>;
};
rng: rng@48021800 {
health-test-magic = <0x17590abc>;
health-test-config = <0xaa74>;
};
ltdc: display-controller@50001000 {
compatible = "st,stm32-ltdc";
reg = <0x50001000 0x200>;
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
status = "disabled";
};
octospi1: octospi@52005000 {
compatible = "st,stm32-ospi";
reg = <0x52005000 0x1000>;
interrupts = <92 0>;
clock-names = "ospix", "ospi-ker";
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00004000>,
<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
octospi2: octospi@5200a000 {
compatible = "st,stm32-ospi";
reg = <0x5200a000 0x1000>;
interrupts = <150 0>;
clock-names = "ospix", "ospi-ker";
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x000080000>,
<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
/* D1 domain, AXI SRAM (128KB with shared ITCM 192KB as `TCM_AXI_SHARED` is `000`) */
sram0: memory@24000000 {
reg = <0x24000000 DT_SIZE_K(320)>;
compatible = "mmio-sram";
};
/* D2 domain, AHB SRAM */
sram1: memory@30000000 {
reg = <0x30000000 DT_SIZE_K(16)>;
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM1";
};
/* D2 domain, AHB SRAM */
sram2: memory@30040000 {
reg = <0x30040000 DT_SIZE_K(16)>;
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM2";
};
/* D3 domain, AHB SRAM */
sram4: memory@38000000 {
reg = <0x38000000 DT_SIZE_K(16)>;
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM4";
};
/* Data TCM RAM */
dtcm: memory@20000000 {
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "DTCM";
};
/* Instruction TCM RAM (64KB as `TCM_AXI_SHARED` is `000`) */
itcm: memory@0 {
compatible = "zephyr,memory-region", "arm,itcm";
reg = <0x00000000 DT_SIZE_K(64)>;
zephyr,memory-region = "ITCM";
};
die_temp: dietemp {
io-channels = <&adc3 17>;
ts-cal2-temp = <130>;
};
};