|  | # Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com> | 
|  | # SPDX-License-Identifier: Apache-2.0 | 
|  |  | 
|  | config PLIC | 
|  | bool "Platform Level Interrupt Controller (PLIC)" | 
|  | default y | 
|  | depends on DT_HAS_SIFIVE_PLIC_1_0_0_ENABLED | 
|  | select MULTI_LEVEL_INTERRUPTS | 
|  | select 2ND_LEVEL_INTERRUPTS | 
|  | help | 
|  | Platform Level Interrupt Controller provides support | 
|  | for external interrupt lines defined by the RISC-V SoC. | 
|  |  | 
|  | if PLIC | 
|  |  | 
|  | config PLIC_SUPPORTS_SOFT_INTERRUPT | 
|  | bool | 
|  | default y | 
|  | depends on DT_HAS_ANDESTECH_NCEPLIC100_ENABLED | 
|  | help | 
|  | Enabled when the PLIC supports software-triggered interrupts. | 
|  |  | 
|  | config PLIC_SUPPORTS_TRIG_TYPE | 
|  | bool | 
|  | default y | 
|  | depends on DT_HAS_ANDESTECH_NCEPLIC100_ENABLED | 
|  | help | 
|  | Enabled when the PLIC supports multiple trigger types, | 
|  | such as level, edge, etc. | 
|  |  | 
|  | if PLIC_SUPPORTS_TRIG_TYPE | 
|  |  | 
|  | config PLIC_TRIG_TYPE_REG_OFFSET | 
|  | hex "Trigger type register offset" | 
|  | default 0x1080 if DT_HAS_ANDESTECH_NCEPLIC100_ENABLED | 
|  | help | 
|  | Offset to the 'trigger type' register. | 
|  |  | 
|  | config PLIC_TRIG_TYPE_BITWIDTH | 
|  | int "Trigger type bitwidth" | 
|  | default 1 | 
|  | help | 
|  | Number of bits required to differentiate between the trigger types. | 
|  |  | 
|  | config PLIC_SUPPORTS_TRIG_EDGE | 
|  | bool | 
|  | default y | 
|  | depends on DT_HAS_ANDESTECH_NCEPLIC100_ENABLED | 
|  | help | 
|  | Enabled when the PLIC supports edge-triggered interrupt. | 
|  |  | 
|  | endif # PLIC_SUPPORTS_TRIG_TYPE | 
|  |  | 
|  | config PLIC_IRQ_AFFINITY | 
|  | bool "Configure IRQ affinity" | 
|  | depends on SMP | 
|  | depends on MP_MAX_NUM_CPUS > 1 | 
|  | help | 
|  | Enable configuration of IRQ affinity. | 
|  |  | 
|  | config PLIC_IRQ_AFFINITY_MASK | 
|  | hex "Default IRQ affinity mask" | 
|  | depends on PLIC_IRQ_AFFINITY | 
|  | default 0x1 | 
|  | help | 
|  | Default mask for the driver when IRQ affinity is enabled. | 
|  |  | 
|  | config PLIC_SHELL | 
|  | bool "PLIC shell commands" | 
|  | depends on SHELL | 
|  | help | 
|  | Enable additional shell commands useful for debugging. | 
|  | Caution: This can use quite a bit of RAM (PLICs * IRQs * sizeof(uint16_t)). | 
|  |  | 
|  | if PLIC_SHELL | 
|  |  | 
|  | config PLIC_SHELL_IRQ_COUNT | 
|  | bool "IRQ count shell commands" | 
|  | default y | 
|  | help | 
|  | Records the number of hits per interrupt line and provide shell commands to access them. | 
|  | Caution: This can use quite a bit of RAM (PLICs * IRQs * sizeof(PLIC_IRQ_COUNT_TYPE)). | 
|  |  | 
|  | config PLIC_SHELL_IRQ_AFFINITY | 
|  | bool "Shell commands to configure IRQ affinity" | 
|  | default y | 
|  | depends on PLIC_IRQ_AFFINITY | 
|  | help | 
|  | Provide shell commands to configure IRQ affinity in runtime. | 
|  |  | 
|  | endif # PLIC_SHELL | 
|  |  | 
|  | endif # PLIC |