dts/arm/aspeed/ast10x0.dtsi

/*
 * SPDX-License-Identifier: Apache-2.0
 *
 * Copyright (c) 2021 ASPEED Technology Inc.
 */

#include <arm/armv7-m.dtsi>
#include <mem.h>
#include <zephyr/dt-bindings/clock/ast10x0_clock.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m4f";
			reg = <0>;
		};
	};

	sram0: memory@0 {
		compatible = "mmio-sram";
	};

	soc {
		syscon: syscon@7e6e2000 {
			compatible = "syscon";
			reg = <0x7e6e2000 0x1000>;
			sysclk: sysclk {
				compatible = "aspeed,ast10x0-clock";
				#clock-cells = <1>;
			};

			sysrst: sysrst {
				compatible = "aspeed,ast10x0-reset";
				#reset-cells = <1>;
			};
		};

		uart5: serial@7e784000 {
			compatible = "ns16550";
			reg = <0x7e784000 0x1000>;
			interrupts = <8 0>;
			clocks = <&sysclk ASPEED_CLK_UART5>;
			status = "disabled";
			reg-shift = <2>;
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};