dts: arm: st: stm32h5: remove U suffix from "resets" in DTSI
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
diff --git a/dts/arm/st/h5/stm32h5.dtsi b/dts/arm/st/h5/stm32h5.dtsi
index d647a1f..87c2fd5 100644
--- a/dts/arm/st/h5/stm32h5.dtsi
+++ b/dts/arm/st/h5/stm32h5.dtsi
@@ -253,7 +253,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
- resets = <&rctl STM32_RESET(APB2, 14U)>;
+ resets = <&rctl STM32_RESET(APB2, 14)>;
interrupts = <58 0>;
status = "disabled";
};
@@ -262,7 +262,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
- resets = <&rctl STM32_RESET(APB1L, 17U)>;
+ resets = <&rctl STM32_RESET(APB1L, 17)>;
interrupts = <59 0>;
status = "disabled";
};
@@ -271,7 +271,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1L, 18U)>;
+ resets = <&rctl STM32_RESET(APB1L, 18)>;
interrupts = <60 0>;
status = "disabled";
};
@@ -280,7 +280,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x44002400 0x400>;
clocks = <&rcc STM32_CLOCK(APB3, 6)>;
- resets = <&rctl STM32_RESET(APB3, 6U)>;
+ resets = <&rctl STM32_RESET(APB3, 6)>;
interrupts = <63 0>;
status = "disabled";
};
@@ -343,7 +343,7 @@
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 11)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 11U)>;
+ resets = <&rctl STM32_RESET(APB2, 11)>;
interrupts = <41 0>, <42 0>, <43 0>, <44 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
status = "disabled";
@@ -360,7 +360,7 @@
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 0)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 0U)>;
+ resets = <&rctl STM32_RESET(APB1L, 0)>;
interrupts = <45 0>;
interrupt-names = "global";
status = "disabled";
@@ -382,7 +382,7 @@
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 1)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 1U)>;
+ resets = <&rctl STM32_RESET(APB1L, 1)>;
interrupts = <46 0>;
interrupt-names = "global";
status = "disabled";
@@ -404,7 +404,7 @@
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 4)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 4U)>;
+ resets = <&rctl STM32_RESET(APB1L, 4)>;
interrupts = <49 0>;
interrupt-names = "global";
status = "disabled";
@@ -426,7 +426,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 5U)>;
+ resets = <&rctl STM32_RESET(APB1L, 5)>;
interrupts = <50 0>;
interrupt-names = "global";
status = "disabled";
@@ -475,7 +475,7 @@
#address-cells = <3>;
#size-cells = <0>;
clocks = <&rcc STM32_CLOCK(APB1, 23)>;
- resets = <&rctl STM32_RESET(APB1L, 23U)>;
+ resets = <&rctl STM32_RESET(APB1L, 23)>;
zephyr,pm-device-runtime-auto;
status = "disabled";
};
@@ -488,7 +488,7 @@
#address-cells = <3>;
#size-cells = <0>;
clocks = <&rcc STM32_CLOCK(APB3, 9)>;
- resets = <&rctl STM32_RESET(APB3, 9U)>;
+ resets = <&rctl STM32_RESET(APB3, 9)>;
zephyr,pm-device-runtime-auto;
status = "disabled";
};
diff --git a/dts/arm/st/h5/stm32h562.dtsi b/dts/arm/st/h5/stm32h562.dtsi
index c095de9..1f30f65 100644
--- a/dts/arm/st/h5/stm32h562.dtsi
+++ b/dts/arm/st/h5/stm32h562.dtsi
@@ -151,7 +151,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
- resets = <&rctl STM32_RESET(APB1L, 19U)>;
+ resets = <&rctl STM32_RESET(APB1L, 19)>;
interrupts = <61 0>;
status = "disabled";
};
@@ -160,7 +160,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
- resets = <&rctl STM32_RESET(APB1L, 20U)>;
+ resets = <&rctl STM32_RESET(APB1L, 20)>;
interrupts = <62 0>;
status = "disabled";
};
@@ -169,7 +169,7 @@
compatible = "st,stm32-uart";
reg = <0x40007800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 30)>;
- resets = <&rctl STM32_RESET(APB1L, 30U)>;
+ resets = <&rctl STM32_RESET(APB1L, 30)>;
interrupts = <98 0>;
status = "disabled";
};
@@ -178,7 +178,7 @@
compatible = "st,stm32-uart";
reg = <0x40007c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 31)>;
- resets = <&rctl STM32_RESET(APB1L, 31U)>;
+ resets = <&rctl STM32_RESET(APB1L, 31)>;
interrupts = <99 0>;
status = "disabled";
};
@@ -187,7 +187,7 @@
compatible = "st,stm32-uart";
reg = <0x40008000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 0)>;
- resets = <&rctl STM32_RESET(APB1H, 0U)>;
+ resets = <&rctl STM32_RESET(APB1H, 0)>;
interrupts = <100 0>;
status = "disabled";
};
@@ -196,7 +196,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40006400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 25)>;
- resets = <&rctl STM32_RESET(APB1L, 25U)>;
+ resets = <&rctl STM32_RESET(APB1L, 25)>;
interrupts = <85 0>;
status = "disabled";
};
@@ -205,7 +205,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40006800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 26)>;
- resets = <&rctl STM32_RESET(APB1L, 26U)>;
+ resets = <&rctl STM32_RESET(APB1L, 26)>;
interrupts = <86 0>;
status = "disabled";
};
@@ -214,7 +214,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40006c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 27)>;
- resets = <&rctl STM32_RESET(APB1L, 27U)>;
+ resets = <&rctl STM32_RESET(APB1L, 27)>;
interrupts = <87 0>;
status = "disabled";
};
@@ -223,7 +223,7 @@
compatible = "st,stm32-uart";
reg = <0x40008400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 1)>;
- resets = <&rctl STM32_RESET(APB1H, 1U)>;
+ resets = <&rctl STM32_RESET(APB1H, 1)>;
interrupts = <101 0>;
status = "disabled";
};
@@ -319,7 +319,7 @@
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 2)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 2U)>;
+ resets = <&rctl STM32_RESET(APB1L, 2)>;
interrupts = <47 0>;
interrupt-names = "global";
status = "disabled";
@@ -341,7 +341,7 @@
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 3)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 3U)>;
+ resets = <&rctl STM32_RESET(APB1L, 3)>;
interrupts = <48 0>;
interrupt-names = "global";
status = "disabled";
@@ -380,7 +380,7 @@
reg = <0x40001800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 6)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 6U)>;
+ resets = <&rctl STM32_RESET(APB1L, 6)>;
interrupts = <120 0>;
interrupt-names = "global";
status = "disabled";
@@ -402,7 +402,7 @@
reg = <0x40001c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 7)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 7U)>;
+ resets = <&rctl STM32_RESET(APB1L, 7)>;
interrupts = <121 0>;
interrupt-names = "global";
status = "disabled";
@@ -424,7 +424,7 @@
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 8)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 8U)>;
+ resets = <&rctl STM32_RESET(APB1L, 8)>;
interrupts = <122 0>;
interrupt-names = "global";
status = "disabled";
@@ -446,7 +446,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 16)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 16U)>;
+ resets = <&rctl STM32_RESET(APB2, 16)>;
interrupts = <71 0>;
interrupt-names = "global";
status = "disabled";
@@ -468,7 +468,7 @@
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 17)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 17U)>;
+ resets = <&rctl STM32_RESET(APB2, 17)>;
interrupts = <72 0>;
interrupt-names = "global";
status = "disabled";
@@ -490,7 +490,7 @@
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 18)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 18U)>;
+ resets = <&rctl STM32_RESET(APB2, 18)>;
interrupts = <73 0>;
interrupt-names = "global";
status = "disabled";
@@ -511,7 +511,7 @@
compatible = "st,stm32-aes";
reg = <0x420c0000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 16)>;
- resets = <&rctl STM32_RESET(AHB2, 16U)>;
+ resets = <&rctl STM32_RESET(AHB2, 16)>;
interrupts = <116 0>;
status = "disabled";
};
@@ -521,7 +521,7 @@
reg = <0x46008000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB4, 11)>,
<&rcc STM32_SRC_PLL1_Q SDMMC1_SEL(0)>;
- resets = <&rctl STM32_RESET(AHB4, 11U)>;
+ resets = <&rctl STM32_RESET(AHB4, 11)>;
interrupts = <79 0>;
status = "disabled";
};
diff --git a/dts/arm/st/h5/stm32h563.dtsi b/dts/arm/st/h5/stm32h563.dtsi
index 8b728fd..8717ec0 100644
--- a/dts/arm/st/h5/stm32h563.dtsi
+++ b/dts/arm/st/h5/stm32h563.dtsi
@@ -15,7 +15,7 @@
reg = <0x46008c00 0x400>;
clocks = <&rcc STM32_CLOCK(AHB4, 12)>,
<&rcc STM32_SRC_PLL1_Q SDMMC2_SEL(0)>;
- resets = <&rctl STM32_RESET(AHB4, 12U)>;
+ resets = <&rctl STM32_RESET(AHB4, 12)>;
interrupts = <102 0>;
status = "disabled";
};
