| /* |
| * Copyright (c) 2023 STMicroelectronics |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <st/h5/stm32h5.dtsi> |
| #include <zephyr/dt-bindings/flash_controller/ospi.h> |
| /* keep both header files for compatibility */ |
| #include <zephyr/dt-bindings/flash_controller/xspi.h> |
| #include <mem.h> |
| |
| / { |
| clocks { |
| /* The pll scheme is similar to stm32u5 */ |
| pll3: pll3 { |
| #clock-cells = <0>; |
| compatible = "st,stm32u5-pll-clock"; |
| status = "disabled"; |
| }; |
| }; |
| |
| soc { |
| compatible = "st,stm32h562", "st,stm32h5", "simple-bus"; |
| |
| pinctrl: pin-controller@42020000 { |
| gpioe: gpio@42021000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42021000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 4)>; |
| }; |
| |
| gpiof: gpio@42021400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42021400 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 5)>; |
| }; |
| |
| gpiog: gpio@42021800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42021800 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 6)>; |
| }; |
| |
| gpioi: gpio@42022000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42022000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 8)>; |
| }; |
| }; |
| |
| sram1: memory@20000000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| reg = <0x20000000 DT_SIZE_K(256)>; |
| zephyr,memory-region = "SRAM1"; |
| }; |
| |
| sram2: memory@20040000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| reg = <0x20040000 DT_SIZE_K(64)>; |
| zephyr,memory-region = "SRAM2"; |
| }; |
| |
| sram3: memory@20050000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| reg = <0x20050000 DT_SIZE_K(320)>; |
| zephyr,memory-region = "SRAM3"; |
| }; |
| |
| backup_sram: memory@40036400 { |
| reg = <0x40036400 DT_SIZE_K(4)>; |
| }; |
| |
| lptim3: timers@44004800 { |
| compatible = "st,stm32-lptim"; |
| clocks = <&rcc STM32_CLOCK(APB3, 12)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x44004800 0x400>; |
| interrupts = <127 1>; |
| interrupt-names = "wakeup"; |
| status = "disabled"; |
| }; |
| |
| lptim4: timers@44004c00 { |
| compatible = "st,stm32-lptim"; |
| clocks = <&rcc STM32_CLOCK(APB3, 13)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x44004c00 0x400>; |
| interrupts = <128 1>; |
| interrupt-names = "wakeup"; |
| status = "disabled"; |
| }; |
| |
| lptim5: timers@44005000 { |
| compatible = "st,stm32-lptim"; |
| clocks = <&rcc STM32_CLOCK(APB3, 14)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x44005000 0x400>; |
| interrupts = <129 1>; |
| interrupt-names = "wakeup"; |
| status = "disabled"; |
| }; |
| |
| lptim6: timers@44005400 { |
| compatible = "st,stm32-lptim"; |
| clocks = <&rcc STM32_CLOCK(APB3, 15)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x44005400 0x400>; |
| interrupts = <130 1>; |
| interrupt-names = "wakeup"; |
| status = "disabled"; |
| }; |
| |
| sai1_a: sai1@40015404 { |
| compatible = "st,stm32-sai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40015404 0x20>; |
| clocks = <&rcc STM32_CLOCK(APB2, 21)>, |
| <&rcc STM32_SRC_PLL2_P SAI1_SEL(0)>; |
| dmas = <&gpdma1 1 53 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | |
| STM32_DMA_16BITS)>; |
| status = "disabled"; |
| }; |
| |
| sai1_b: sai1@40015424 { |
| compatible = "st,stm32-sai"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40015424 0x20>; |
| clocks = <&rcc STM32_CLOCK(APB2, 21)>, |
| <&rcc STM32_SRC_PLL2_P SAI1_SEL(0)>; |
| dmas = <&gpdma1 0 54 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH | |
| STM32_DMA_16BITS)>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@40004c00 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40004c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 19)>; |
| resets = <&rctl STM32_RESET(APB1L, 19)>; |
| interrupts = <61 0>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@40005000 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40005000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 20)>; |
| resets = <&rctl STM32_RESET(APB1L, 20)>; |
| interrupts = <62 0>; |
| status = "disabled"; |
| }; |
| |
| uart7: serial@40007800 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40007800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 30)>; |
| resets = <&rctl STM32_RESET(APB1L, 30)>; |
| interrupts = <98 0>; |
| status = "disabled"; |
| }; |
| |
| uart8: serial@40007c00 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40007c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 31)>; |
| resets = <&rctl STM32_RESET(APB1L, 31)>; |
| interrupts = <99 0>; |
| status = "disabled"; |
| }; |
| |
| uart9: serial@40008000 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40008000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 0)>; |
| resets = <&rctl STM32_RESET(APB1H, 0)>; |
| interrupts = <100 0>; |
| status = "disabled"; |
| }; |
| |
| usart6: serial@40006400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40006400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 25)>; |
| resets = <&rctl STM32_RESET(APB1L, 25)>; |
| interrupts = <85 0>; |
| status = "disabled"; |
| }; |
| |
| usart10: serial@40006800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40006800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 26)>; |
| resets = <&rctl STM32_RESET(APB1L, 26)>; |
| interrupts = <86 0>; |
| status = "disabled"; |
| }; |
| |
| usart11: serial@40006c00 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40006c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 27)>; |
| resets = <&rctl STM32_RESET(APB1L, 27)>; |
| interrupts = <87 0>; |
| status = "disabled"; |
| }; |
| |
| uart12: serial@40008400 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40008400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 1)>; |
| resets = <&rctl STM32_RESET(APB1H, 1)>; |
| interrupts = <101 0>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@44002800 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x44002800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB3, 7)>; |
| interrupts = <80 0>, <81 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@44002c00 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x44002c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB3, 8)>; |
| interrupts = <125 0>, <126 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| spi4: spi@40014c00 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40014c00 0x400>; |
| interrupts = <82 5>; |
| clocks = <&rcc STM32_CLOCK(APB2, 19)>; |
| status = "disabled"; |
| }; |
| |
| spi5: spi@44002000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x44002000 0x400>; |
| interrupts = <83 5>; |
| clocks = <&rcc STM32_CLOCK(APB3, 5)>; |
| status = "disabled"; |
| }; |
| |
| spi6: spi@40015000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40015000 0x400>; |
| interrupts = <84 5>; |
| clocks = <&rcc STM32_CLOCK(APB2, 20)>; |
| status = "disabled"; |
| }; |
| |
| xspi1: spi@47001400 { |
| compatible = "st,stm32-xspi"; |
| reg = <0x47001400 0x400>, <0x90000000 DT_SIZE_M(256)>; |
| interrupts = <78 0>; |
| clock-names = "xspix", "xspi-ker"; |
| clocks = <&rcc STM32_CLOCK(AHB4, 20)>, |
| <&rcc STM32_SRC_PLL1_Q OCTOSPI1_SEL(1)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| adc2: adc@42028100 { |
| compatible = "st,stm32-adc"; |
| reg = <0x42028100 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 10)>; |
| interrupts = <69 0>; |
| vref-mv = <3300>; |
| #io-channel-cells = <1>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x02) |
| STM32_ADC_RES(6, 0x03)>; |
| sampling-times = <3 7 13 25 48 93 248 641>; |
| st,adc-sequencer = "FULLY_CONFIGURABLE"; |
| st,adc-oversampler = "OVERSAMPLER_MINIMAL"; |
| st,adc-internal-regulator = "startup-sw-delay"; |
| st,adc-has-deep-powerdown; |
| st,adc-has-differential-support; |
| status = "disabled"; |
| }; |
| |
| timers4: timers@40000800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 2)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1L, 2)>; |
| interrupts = <47 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers5: timers@40000c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 3)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1L, 3)>; |
| interrupts = <48 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers8: timers@40013400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40013400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 13)>, |
| <&rcc STM32_SRC_TIMPCLK2 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB2, 13)>; |
| interrupts = <65 0>, <66 0>, <67 0>, <68 0>; |
| interrupt-names = "brk", "up", "trgcom", "cc"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers12: timers@40001800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 6)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1L, 6)>; |
| interrupts = <120 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers13: timers@40001c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 7)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1L, 7)>; |
| interrupts = <121 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers14: timers@40002000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40002000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 8)>, |
| <&rcc STM32_SRC_TIMPCLK1 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB1L, 8)>; |
| interrupts = <122 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers15: timers@40014000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 16)>, |
| <&rcc STM32_SRC_TIMPCLK2 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB2, 16)>; |
| interrupts = <71 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers16: timers@40014400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 17)>, |
| <&rcc STM32_SRC_TIMPCLK2 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB2, 17)>; |
| interrupts = <72 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers17: timers@40014800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 18)>, |
| <&rcc STM32_SRC_TIMPCLK2 NO_SEL>; |
| resets = <&rctl STM32_RESET(APB2, 18)>; |
| interrupts = <73 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| aes: aes@420c0000 { |
| compatible = "st,stm32-aes"; |
| reg = <0x420c0000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 16)>; |
| resets = <&rctl STM32_RESET(AHB2, 16)>; |
| interrupts = <116 0>; |
| status = "disabled"; |
| }; |
| |
| sdmmc1: sdmmc@46008000 { |
| compatible = "st,stm32-sdmmc"; |
| reg = <0x46008000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 11)>, |
| <&rcc STM32_SRC_PLL1_Q SDMMC1_SEL(0)>; |
| resets = <&rctl STM32_RESET(AHB4, 11)>; |
| interrupts = <79 0>; |
| status = "disabled"; |
| }; |
| |
| fmc: memory-controller@47000400 { |
| compatible = "st,stm32-fmc"; |
| reg = <0x47000400 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 16)>; |
| status = "disabled"; |
| }; |
| }; |
| |
| smbus3: smbus3 { |
| compatible = "st,stm32-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c = <&i2c3>; |
| status = "disabled"; |
| }; |
| |
| smbus4: smbus4 { |
| compatible = "st,stm32-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c = <&i2c4>; |
| status = "disabled"; |
| }; |
| }; |
