dts/xtensa/sample_controller32.dtsi

/*
 * Copyright (c) 2019 Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include "skeleton.dtsi"

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "sample_controller";
			reg = <0>;
		};
	};

	sram0: memory@60000000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x60000000 0x4000000>;
	};

	srom0: memory@fe000000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x50000000 0x1000000>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

	};
};