| description: Atmel SAM0 SERCOM UART driver |
| |
| compatible: "atmel,sam0-uart" |
| |
| include: |
| - name: uart-controller.yaml |
| - name: pinctrl-device.yaml |
| |
| properties: |
| reg: |
| required: true |
| |
| interrupts: |
| required: true |
| |
| clocks: |
| required: true |
| |
| clock-names: |
| required: true |
| |
| rxpo: |
| type: int |
| required: true |
| description: | |
| Receive Data Pinout. An enumeration with the following values: |
| |
| +-------+---------------+ |
| | Value | RX Pin | |
| +-------+---------------+ |
| | 0 | SERCOM_PAD[0] | |
| +-------+---------------+ |
| | 1 | SERCOM_PAD[1] | |
| +-------+---------------+ |
| | 2 | SERCOM_PAD[2] | |
| +-------+---------------+ |
| | 3 | SERCOM_PAD[3] | |
| +-------+---------------+ |
| |
| |
| txpo: |
| type: int |
| required: true |
| description: | |
| Transmit Data Pinout. An enumeration with values that depend on the |
| hardware being used. This controls both the transmit pins and if |
| hardware flow control is used. |
| |
| SAMD20: |
| |
| +-------+---------------+ |
| | Value | TX Pin | |
| +-------+---------------+ |
| | 0 | SERCOM_PAD[0] | |
| +-------+---------------+ |
| | 1 | SERCOM_PAD[2] | |
| +-------+---------------+ |
| |
| SAMD21/DA21/R21: |
| |
| +-------+---------------+---------------+---------------+ |
| | Value | TX Pin | RTS | CTS | |
| +-------+---------------+---------------+---------------+ |
| | 0 | SERCOM_PAD[0] | N/A | N/A | |
| +-------+---------------+---------------+---------------+ |
| | 1 | SERCOM_PAD[2] | N/A | N/A | |
| +-------+---------------+---------------+---------------+ |
| | 2 | SERCOM_PAD[0] | SERCOM_PAD[2] | SERCOM_PAD[3] | |
| +-------+---------------+---------------+---------------+ |
| | 3 | Reserved | |
| +-------+-----------------------------------------------+ |
| |
| SAML2x/C2x: |
| |
| +-------+----------------+---------------+--------------+ |
| | Value | TX Pin | RTS | CTS | |
| +-------+---------------+---------------+---------------+ |
| | 0 | SERCOM_PAD[0] | N/A | N/A | |
| +-------+---------------+---------------+---------------+ |
| | 1 | SERCOM_PAD[2] | N/A | N/A | |
| +-------+---------------+---------------+---------------+ |
| | 2 | SERCOM_PAD[0] | SERCOM_PAD[2] | SERCOM_PAD[3] | |
| +-------+---------------+---------------+---------------+ |
| | 3 | SERCOM_PAD[0] | SERCOM_PAD[2] | N/A | |
| +-------+---------------+---------------+---------------+ |
| |
| SAMD5/E5: |
| |
| +-------+---------------+---------------+---------------+ |
| | Value | TX Pin | RTS | CTS | |
| +-------+---------------+---------------+---------------+ |
| | 0 | SERCOM_PAD[0] | N/A | N/A | |
| +-------+---------------+---------------+---------------+ |
| | 1 | Reserved | |
| +-------+---------------+---------------+---------------+ |
| | 2 | SERCOM_PAD[0] | SERCOM_PAD[2] | SERCOM_PAD[3] | |
| +-------+---------------+---------------+---------------+ |
| | 3 | SERCOM_PAD[0] | SERCOM_PAD[2] | N/A | |
| +-------+---------------+---------------+---------------+ |
| |
| |
| collision-detection: |
| type: boolean |
| description: Enable collision detection for half-duplex mode. |
| |
| dmas: |
| description: | |
| Optional TX & RX dma specifiers. Each specifier will have a phandle |
| reference to the dmac controller, the channel number, and peripheral |
| trigger source. |
| |
| For example dmas for TX, RX on SERCOM3 |
| dmas = <&dmac 0 0xb>, <&dmac 0 0xa>; |
| |
| dma-names: |
| description: | |
| Required if the dmas property exists. This should be "tx" and "rx" |
| to match the dmas property. |
| |
| For example |
| dma-names = "tx", "rx"; |