| /* |
| * Copyright (c) 2025 Silicon Laboratories Inc. |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv8-m.dtsi> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/i2c/i2c.h> |
| #include <dt-bindings/adc/adc.h> |
| #include <dt-bindings/clock/silabs/xg29-clock.h> |
| #include <dt-bindings/dma/silabs/xg29-dma.h> |
| #include <freq.h> |
| |
| / { |
| chosen { |
| zephyr,flash-controller = &msc; |
| zephyr,entropy = &se; |
| }; |
| |
| clocks { |
| hfxort: hfxort { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&hfxo>; |
| }; |
| |
| hfrcodpllrt: hfrcodpllrt { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&hfrcodpll>; |
| }; |
| |
| sysclk: sysclk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&hfrcodpll>; |
| }; |
| |
| hclk: hclk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&sysclk>; |
| /* Divisors 1, 2, 4, 8, 16 allowed */ |
| clock-div = <1>; |
| }; |
| |
| pclk: pclk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&hclk>; |
| /* Divisors 1, 2 allowed */ |
| clock-div = <2>; |
| }; |
| |
| lspclk: lspclk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&pclk>; |
| /* Fixed divisor of 2 */ |
| clock-div = <2>; |
| }; |
| |
| hclkdiv1024: hclkdiv1024 { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&hclk>; |
| /* Fixed divisor of 1024 */ |
| clock-div = <1024>; |
| }; |
| |
| traceclk: traceclk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&sysclk>; |
| /* Divisors 1, 2, 3, 4 allowed */ |
| clock-div = <1>; |
| }; |
| |
| em01grpaclk: em01grpaclk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&hfrcodpll>; |
| }; |
| |
| em01grpbclk: em01grpbclk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&hfrcodpll>; |
| }; |
| |
| em01grpcclk: em01grpcclk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&hfrcodpll>; |
| }; |
| |
| iadcclk: iadcclk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&em01grpaclk>; |
| }; |
| |
| em23grpaclk: em23grpaclk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&lfrco>; |
| }; |
| |
| em4grpaclk: em4grpaclk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&lfrco>; |
| }; |
| |
| rtccclk: rtccclk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&lfrco>; |
| }; |
| |
| wdog0clk: wdog0clk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&lfrco>; |
| }; |
| |
| systickclk: systickclk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&hclk>; |
| }; |
| |
| eusart0clk: eusart0clk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&em01grpaclk>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m33"; |
| reg = <0>; |
| cpu-power-states = <&pstate_em1 &pstate_em2>; |
| /* |
| * The minimum residency and exit latency is |
| * managed by sl_power_manager on S2 devices. |
| */ |
| }; |
| |
| power-states { |
| /* |
| * EM1 is a basic "CPU WFI idle", all high-freq clocks remain |
| * enabled. |
| */ |
| pstate_em1: em1 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "runtime-idle"; |
| /* HFXO remains active */ |
| }; |
| |
| /* |
| * EM2 is a deepsleep with HF clocks disabled by HW, voltages |
| * scaled down, etc. |
| */ |
| pstate_em2: em2 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| }; |
| }; |
| }; |
| |
| sram0: memory@20000000 { |
| device_type = "memory"; |
| compatible = "mmio-sram"; |
| }; |
| |
| soc { |
| cmu: clock@50008000 { |
| compatible = "silabs,series-clock"; |
| reg = <0x50008000 0x4000>; |
| interrupts = <52 0>; |
| interrupt-names = "cmu"; |
| status = "okay"; |
| #clock-cells = <2>; |
| }; |
| |
| hfxo: hfxo@5000c000 { |
| #clock-cells = <0>; |
| compatible = "silabs,hfxo"; |
| reg = <0x5000c000 0x4000>; |
| interrupts = <50 0>; |
| interrupt-names = "hfxo0"; |
| clock-frequency = <DT_FREQ_K(38400)>; |
| ctune = <140>; |
| precision = <50>; |
| status = "disabled"; |
| }; |
| |
| hfrcodpll: hfrcodpll@50010000 { |
| #clock-cells = <0>; |
| compatible = "silabs,series2-hfrcodpll"; |
| reg = <0x50010000 0x4000>; |
| interrupts = <51 0>, <56 0>; |
| interrupt-names = "hfrco0", "dpll0"; |
| clock-frequency = <DT_FREQ_M(19)>; |
| }; |
| |
| fsrco: fsrco@50018000 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| reg = <0x50018000 0x4000>; |
| clock-frequency = <DT_FREQ_M(20)>; |
| }; |
| |
| lfxo: lfxo@50020000 { |
| #clock-cells = <0>; |
| compatible = "silabs,series2-lfxo"; |
| reg = <0x50020000 0x4000>; |
| interrupts = <27 0>; |
| interrupt-names = "lfxo"; |
| clock-frequency = <32768>; |
| ctune = <63>; |
| precision = <50>; |
| timeout = <4096>; |
| status = "disabled"; |
| }; |
| |
| lfrco: lfrco@50024000 { |
| #clock-cells = <0>; |
| compatible = "silabs,series2-lfrco"; |
| reg = <0x50024000 0x4000>; |
| interrupts = <28 0>; |
| interrupt-names = "lfrco"; |
| clock-frequency = <32768>; |
| }; |
| |
| ulfrco: ulfrco@50028000 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| reg = <0x50028000 0x4000>; |
| interrupts = <29 0>; |
| interrupt-names = "ulfrco"; |
| clock-frequency = <1000>; |
| }; |
| |
| clkin0: clkin0@5003c460 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| reg = <0x5003c460 0x4>; |
| clock-frequency = <DT_FREQ_M(38)>; |
| }; |
| |
| msc: flash-controller@50030000 { |
| compatible = "silabs,series2-flash-controller"; |
| reg = <0x50030000 0x4000>; |
| interrupts = <55 0>; |
| interrupt-names = "msc"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "soc-nv-flash"; |
| write-block-size = <4>; |
| erase-block-size = <8192>; |
| }; |
| }; |
| |
| gpio: gpio@5003c000 { |
| compatible = "silabs,gecko-gpio"; |
| reg = <0x5003C000 0x440>; |
| interrupts = <31 0>, <30 0>; |
| interrupt-names = "GPIO_EVEN", "GPIO_ODD"; |
| clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>; |
| ranges; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| gpioa: gpio@5003c000 { |
| compatible = "silabs,gecko-gpio-port"; |
| reg = <0x5003C000 0x30>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpiob: gpio@5003c030 { |
| compatible = "silabs,gecko-gpio-port"; |
| reg = <0x5003C030 0x30>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpioc: gpio@5003c060 { |
| compatible = "silabs,gecko-gpio-port"; |
| reg = <0x5003C060 0x30>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gpiod: gpio@5003c090 { |
| compatible = "silabs,gecko-gpio-port"; |
| reg = <0x5003C090 0x30>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| pinctrl: pin-controller@5003c440 { |
| compatible = "silabs,dbus-pinctrl"; |
| reg = <0x5003c440 0xbc0>, <0x5003c320 0x40>; |
| reg-names = "dbus", "abus"; |
| }; |
| |
| dma0: dma@40040000{ |
| compatible = "silabs,ldma"; |
| reg = <0x40040000 0x4000>; |
| interrupts = <26 0>; |
| interrupt-names = "ldma"; |
| #dma-cells = <1>; |
| dma_channels = <8>; |
| status = "disabled"; |
| }; |
| |
| usart0: usart@5005c000 { |
| compatible = "silabs,usart-uart"; |
| reg = <0x5005C000 0x400>; |
| interrupts = <16 0>, <17 0>; |
| interrupt-names = "rx", "tx"; |
| clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>; |
| status = "disabled"; |
| }; |
| |
| usart1: usart@50060000 { |
| compatible = "silabs,usart-uart"; |
| reg = <0x50060000 0x400>; |
| interrupts = <18 0>, <19 0>; |
| interrupt-names = "rx", "tx"; |
| clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>; |
| status = "disabled"; |
| }; |
| |
| burtc0: burtc@50064000 { |
| compatible = "silabs,gecko-burtc"; |
| reg = <0x50064000 0x4000>; |
| interrupts = <23 0>; |
| interrupt-names = "burtc"; |
| clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@5a010000 { |
| compatible = "silabs,gecko-i2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| reg = <0x5a010000 0x4000>; |
| interrupts = <32 0>; |
| interrupt-names = "i2c0"; |
| clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@50068000 { |
| compatible = "silabs,gecko-i2c"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| reg = <0x50068000 0x4000>; |
| interrupts = <33 0>; |
| interrupt-names = "i2c1"; |
| clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| dcdc: dcdc@50094000 { |
| compatible = "silabs,series2-dcdc"; |
| reg = <0x50094000 0x4000>; |
| interrupts = <8 0>; |
| interrupt-names = "dcdc"; |
| status = "disabled"; |
| }; |
| |
| eusart0: eusart@5a040000 { |
| compatible = "silabs,eusart-spi"; |
| reg = <0x5A040000 0x4000>; |
| interrupts = <20 0>, <21 0>; |
| interrupt-names = "rx", "tx"; |
| clocks = <&cmu CLOCK_EUSART0 CLOCK_BRANCH_EUSART0CLK>; |
| status = "disabled"; |
| }; |
| |
| eusart1: eusart@500b4000 { |
| compatible = "silabs,eusart-spi"; |
| reg = <0x500B4000 0x4000>; |
| interrupts = <68 0>, <69 0>; |
| interrupt-names = "rx", "tx"; |
| clocks = <&cmu CLOCK_EUSART1 CLOCK_BRANCH_EM01GRPCCLK>; |
| status = "disabled"; |
| }; |
| |
| rtcc0: rtcc@58000000 { |
| compatible = "silabs,gecko-stimer"; |
| reg = <0x58000000 0x4000>; |
| interrupts = <15 0>; |
| interrupt-names = "rtcc"; |
| clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>; |
| clock-frequency = <32768>; |
| prescaler = <1>; |
| status = "disabled"; |
| }; |
| |
| wdog0: wdog@58018000 { |
| compatible = "silabs,gecko-wdog"; |
| reg = <0x58018000 0x4000>; |
| peripheral-id = <0>; |
| interrupts = <49 0>; |
| interrupt-names = "wdog0"; |
| clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>; |
| status = "disabled"; |
| }; |
| |
| adc0: adc@5a004000 { |
| compatible = "silabs,gecko-iadc"; |
| reg = <0x5a004000 0x4000>; |
| interrupts = <54 0>; |
| interrupt-names = "iadc0"; |
| clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| }; |
| |
| acmp0: acmp@5a008000 { |
| compatible = "silabs,acmp"; |
| reg = <0x5a008000 0x4000>; |
| interrupts = <48 0>; |
| clocks = <&cmu CLOCK_ACMP0 CLOCK_BRANCH_EM01GRPACLK>; |
| status = "disabled"; |
| }; |
| |
| se: semailbox@4c000000 { |
| compatible = "silabs,gecko-semailbox"; |
| reg = <0x4c000000 0x1000>; |
| interrupts = <0 3>, <1 3>, <2 3>; |
| interrupt-names = "SETAMPERHOST", "SEMBRX", "SEMBTX"; |
| status = "disabled"; |
| }; |
| |
| radio: radio@b0000000 { |
| compatible = "silabs,series2-radio"; |
| reg = <0xb0000000 0x1000000>; |
| interrupts = <36 0>, <37 0>, <38 0>, <39 0>, <40 0>, <41 0>, |
| <42 0>, <43 0>, <44 0>, <45 0>, <46 0>, <47 0>; |
| interrupt-names = "agc", "bufc", "frc_pri", "frc", "modem", "protimer", |
| "rac_rsm", "rac_seq", "rdmailbox", "rfsense", "synth", |
| "prortc"; |
| pa-initial-power-dbm = <10>; |
| pa-ramp-time-us = <2>; |
| pa-voltage-mv = <3300>; |
| pa-2p4ghz = "highest"; |
| |
| bt_hci_silabs: bt_hci_silabs { |
| compatible = "silabs,bt-hci-efr32"; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| hwinfo: hwinfo { |
| compatible = "silabs,series2-hwinfo"; |
| status = "disabled"; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
