| /* |
| * Copyright (c) 2019 Linaro Limited |
| * Copyright (c) 2019 Centaur Analytics, Inc |
| * Copyright (c) 2024 STMicroelectronics |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv7-m.dtsi> |
| #include <zephyr/dt-bindings/clock/stm32wb_clock.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/pwm/pwm.h> |
| #include <zephyr/dt-bindings/adc/adc.h> |
| #include <zephyr/dt-bindings/pwm/stm32_pwm.h> |
| #include <zephyr/dt-bindings/dma/stm32_dma.h> |
| #include <zephyr/dt-bindings/adc/stm32l4_adc.h> |
| #include <zephyr/dt-bindings/reset/stm32wb_l_reset.h> |
| #include <zephyr/dt-bindings/power/stm32_pwr.h> |
| #include <freq.h> |
| |
| / { |
| chosen { |
| zephyr,entropy = &rng; |
| zephyr,flash-controller = &flash; |
| zephyr,bt-hci = &ble_rf; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m4f"; |
| reg = <0>; |
| cpu-power-states = <&stop0 &stop1 &stop2>; |
| }; |
| |
| power-states { |
| stop0: state0 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <1>; |
| min-residency-us = <100>; |
| }; |
| stop1: state1 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <2>; |
| min-residency-us = <500>; |
| }; |
| stop2: state2 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <3>; |
| min-residency-us = <900>; |
| }; |
| }; |
| }; |
| |
| sram0: memory@20000000 { |
| compatible = "mmio-sram"; |
| }; |
| |
| sram1: memory@20030000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| reg = <0x20030000 0x2800>; |
| zephyr,memory-region = "SRAM1"; |
| }; |
| |
| sram2: memory@20038000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| reg = <0x20038000 0x5000>; |
| zephyr,memory-region = "SRAM2"; |
| }; |
| |
| clocks { |
| clk_hse: clk-hse { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| /* Expected clock-frequency on the whole series 32MHz */ |
| clock-frequency = <DT_FREQ_M(32)>; |
| status = "disabled"; |
| }; |
| |
| clk_hsi: clk-hsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(16)>; |
| status = "disabled"; |
| }; |
| |
| clk_hsi48: clk-hsi48 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(48)>; |
| status = "disabled"; |
| }; |
| |
| clk_msi: clk-msi { |
| #clock-cells = <0>; |
| compatible = "st,stm32-msi-clock"; |
| msi-range = <6>; /* 4MHz (reset value) */ |
| status = "disabled"; |
| }; |
| |
| clk_lse: clk-lse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-lse-clock"; |
| clock-frequency = <32768>; |
| driving-capability = <0>; |
| status = "disabled"; |
| }; |
| |
| clk_lsi1: clk-lsi1 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_K(32)>; |
| status = "disabled"; |
| }; |
| |
| clk_lsi2: clk-lsi2 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_K(32)>; |
| status = "disabled"; |
| }; |
| |
| pll: pll { |
| #clock-cells = <0>; |
| compatible = "st,stm32wb-pll-clock"; |
| status = "disabled"; |
| }; |
| |
| clk48: clk48 { |
| #clock-cells = <0>; |
| compatible = "st,stm32-clock-mux"; |
| status = "disabled"; |
| }; |
| }; |
| |
| soc { |
| flash: flash-controller@58004000 { |
| compatible = "st,stm32-flash-controller", "st,stm32wb-flash-controller"; |
| reg = <0x58004000 0x400>; |
| interrupts = <4 0>; |
| clocks = <&rcc STM32_CLOCK(AHB3, 25U)>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "st,stm32-nv-flash", "soc-nv-flash"; |
| |
| write-block-size = <8>; |
| erase-block-size = <4096>; |
| /* maximum erase time(ms) for a 4K sector */ |
| max-erase-time = <25>; |
| }; |
| }; |
| |
| rcc: rcc@58000000 { |
| compatible = "st,stm32wb-rcc"; |
| #clock-cells = <2>; |
| reg = <0x58000000 0x400>; |
| |
| rctl: reset-controller { |
| compatible = "st,stm32-rcc-rctl"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| exti: interrupt-controller@58000800 { |
| compatible = "st,stm32-exti"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| #address-cells = <1>; |
| reg = <0x58000800 0x400>; |
| num-lines = <16>; |
| interrupts = <6 0>, <7 0>, <8 0>, <9 0>, |
| <10 0>, <23 0>, <40 0>; |
| interrupt-names = "line0", "line1", "line2", "line3", |
| "line4", "line5-9", "line10-15"; |
| line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, |
| <4 1>, <5 5>, <10 6>; |
| }; |
| |
| pinctrl: pin-controller@48000000 { |
| compatible = "st,stm32-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x48000000 0x2000>; |
| |
| gpioa: gpio@48000000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; |
| }; |
| |
| gpiob: gpio@48000400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000400 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; |
| }; |
| |
| gpioc: gpio@48000800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000800 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; |
| }; |
| |
| gpiod: gpio@48000c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 3U)>; |
| }; |
| |
| gpioe: gpio@48001000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <5>; |
| reg = <0x48001000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 4U)>; |
| }; |
| |
| gpioh: gpio@48001c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <4>; |
| reg = <0x48001c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; |
| }; |
| }; |
| |
| wwdg: watchdog@40002c00 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x40002C00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 11U)>; |
| interrupts = <0 7>; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@40013800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40013800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 14U)>; |
| resets = <&rctl STM32_RESET(APB2, 14U)>; |
| interrupts = <36 0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 21U)>; |
| interrupts = <30 0>, <31 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@40005c00 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 23U)>; |
| interrupts = <32 0>, <33 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| rtc: rtc@40002800 { |
| compatible = "st,stm32-rtc"; |
| reg = <0x40002800 0x400>; |
| interrupts = <41 0>; |
| clocks = <&rcc STM32_CLOCK(APB1, 10U)>; |
| prescaler = <32768>; |
| alarms-count = <2>; |
| alrm-exti-line = <17>; |
| status = "disabled"; |
| |
| bbram: backup_regs { |
| compatible = "st,stm32-bbram"; |
| st,backup-regs = <20>; |
| status = "disabled"; |
| }; |
| }; |
| |
| spi1: spi@40013000 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| interrupts = <34 5>; |
| clocks = <&rcc STM32_CLOCK(APB2, 12U)>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@40003800 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003800 0x400>; |
| interrupts = <35 5>; |
| clocks = <&rcc STM32_CLOCK(APB1, 14U)>; |
| status = "disabled"; |
| }; |
| |
| lpuart1: serial@40008000 { |
| compatible = "st,stm32-lpuart", "st,stm32-uart"; |
| reg = <0x40008000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>; |
| resets = <&rctl STM32_RESET(APB1H, 0U)>; |
| interrupts = <37 0>; |
| status = "disabled"; |
| }; |
| |
| timers1: timers@40012c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40012c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 11U)>; |
| resets = <&rctl STM32_RESET(APB2, 11U)>; |
| interrupts = <24 0>, <25 0>, <26 0>, <27 0>; |
| interrupt-names = "brk", "up", "trgcom", "cc"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers2: timers@40000000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 0U)>; |
| resets = <&rctl STM32_RESET(APB1L, 0U)>; |
| interrupts = <28 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers16: timers@40014400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 17U)>; |
| resets = <&rctl STM32_RESET(APB2, 17U)>; |
| interrupts = <25 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers17: timers@40014800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 18U)>; |
| resets = <&rctl STM32_RESET(APB2, 18U)>; |
| interrupts = <26 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| adc1: adc@50040000 { |
| compatible = "st,stm32-adc"; |
| reg = <0x50040000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; |
| interrupts = <18 0>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x02) |
| STM32_ADC_RES(6, 0x03)>; |
| sampling-times = <3 7 13 25 48 93 248 641>; |
| st,adc-sequencer = "FULLY_CONFIGURABLE"; |
| st,adc-oversampler = "OVERSAMPLER_MINIMAL"; |
| }; |
| |
| iwdg: watchdog@40003000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x40003000 0x400>; |
| status = "disabled"; |
| }; |
| |
| lptim1: timers@40007c00 { |
| compatible = "st,stm32-lptim"; |
| clocks = <&rcc STM32_CLOCK(APB1, 31U)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40007c00 0x400>; |
| interrupts = <47 1>; |
| interrupt-names = "wakeup"; |
| status = "disabled"; |
| }; |
| |
| dma1: dma@40020000 { |
| compatible = "st,stm32-dma-v2"; |
| #dma-cells = <3>; |
| reg = <0x40020000 0x400>; |
| interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; |
| dma-requests = <7>; |
| dma-offset = <0>; |
| status = "disabled"; |
| }; |
| |
| dma2: dma@40020400 { |
| compatible = "st,stm32-dma-v2"; |
| #dma-cells = <3>; |
| reg = <0x40020400 0x400>; |
| interrupts = <55 0 56 0 57 0 58 0 59 0 60 0 61 0>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; |
| dma-requests = <7>; |
| dma-offset = <7>; |
| status = "disabled"; |
| }; |
| |
| dmamux1: dmamux@40020800 { |
| compatible = "st,stm32-dmamux"; |
| #dma-cells = <3>; |
| reg = <0x40020800 0x400>; |
| interrupts = <62 0>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; |
| dma-channels = <14>; |
| dma-generators = <4>; |
| dma-requests= <36>; |
| status = "disabled"; |
| }; |
| |
| usb: usb@40006800 { |
| compatible = "st,stm32-usb"; |
| reg = <0x40006800 0x400>; |
| interrupts = <20 0>, <19 0>; |
| interrupt-names = "usb", "usbhp"; |
| num-bidir-endpoints = <8>; |
| ram-size = <1024>; |
| phys = <&usb_fs_phy>; |
| clocks = <&rcc STM32_CLOCK(APB1, 26U)>, |
| <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; |
| status = "disabled"; |
| }; |
| |
| quadspi: spi@a0001000 { |
| compatible = "st,stm32-qspi"; |
| #address-cells = <0x1>; |
| #size-cells = <0x0>; |
| reg = <0xa0001000 0x400>; |
| interrupts = <0x32 0x0>; |
| clocks = <&rcc STM32_CLOCK(AHB3, 8U)>; |
| status = "disabled"; |
| }; |
| |
| rng: rng@58001000 { |
| compatible = "st,stm32-rng"; |
| reg = <0x58001000 0x400>; |
| interrupts = <53 0>; |
| clocks = <&rcc STM32_CLOCK(AHB3, 18U)>; |
| status = "disabled"; |
| }; |
| |
| aes1: aes@50060000 { |
| compatible = "st,stm32-aes"; |
| reg = <0x50060000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 16U)>; |
| resets = <&rctl STM32_RESET(AHB2, 16U)>; |
| interrupts = <51 0>; |
| status = "disabled"; |
| }; |
| |
| pwr: power@58000400 { |
| compatible = "st,stm32-pwr"; |
| reg = <0x58000400 0x400>; /* PWR register bank */ |
| status = "disabled"; |
| |
| wkup-pins-nb = <5>; /* 5 system wake-up pins */ |
| wkup-pins-pol; |
| wkup-pins-pupd; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| wkup-pin@1 { |
| reg = <0x1>; |
| wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>; |
| }; |
| |
| wkup-pin@4 { |
| reg = <0x4>; |
| wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>; |
| }; |
| }; |
| }; |
| |
| die_temp: dietemp { |
| compatible = "st,stm32-temp-cal"; |
| ts-cal1-addr = <0x1FFF75A8>; |
| ts-cal2-addr = <0x1FFF75CA>; |
| ts-cal1-temp = <30>; |
| ts-cal2-temp = <130>; |
| ts-cal-vrefanalog = <3000>; |
| io-channels = <&adc1 17>; |
| status = "disabled"; |
| }; |
| |
| vref: vref { |
| compatible = "st,stm32-vref"; |
| vrefint-cal-addr = <0x1FFF75AA>; |
| vrefint-cal-mv = <3600>; |
| io-channels = <&adc1 0>; |
| status = "disabled"; |
| }; |
| |
| vbat: vbat { |
| compatible = "st,stm32-vbat"; |
| ratio = <3>; |
| io-channels = <&adc1 18>; |
| status = "disabled"; |
| }; |
| |
| usb_fs_phy: usbphy { |
| compatible = "usb-nop-xceiv"; |
| #phy-cells = <0>; |
| }; |
| |
| ble_rf: ble_rf { |
| compatible = "st,stm32wb-rf"; |
| clocks = <&rcc STM32_CLOCK(AHB3, 20U)>, |
| <&rcc STM32_SRC_LSE RFWKP_SEL(1)>; |
| }; |
| |
| smbus1: smbus1 { |
| compatible = "st,stm32-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c = <&i2c1>; |
| status = "disabled"; |
| }; |
| |
| smbus3: smbus3 { |
| compatible = "st,stm32-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c = <&i2c3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
