| /* |
| * Copyright 2022,2024 NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <mem.h> |
| #include <freq.h> |
| #include <arm64/armv8-a.dtsi> |
| #include <zephyr/dt-bindings/clock/imx_ccm.h> |
| #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> |
| #include <zephyr/dt-bindings/rdc/imx_rdc.h> |
| |
| / { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| chosen { |
| zephyr,console = &uart2; |
| zephyr,shell-uart = &uart2; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0>; |
| }; |
| |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <1>; |
| }; |
| |
| cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <2>; |
| }; |
| |
| cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <3>; |
| }; |
| |
| }; |
| |
| arch_timer: timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| gic: interrupt-controller@38800000 { |
| compatible = "arm,gic-v3", "arm,gic"; |
| reg = <0x38800000 0x10000>, /* GIC Dist */ |
| <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| status = "okay"; |
| }; |
| |
| gpio1: gpio@30200000 { |
| compatible = "nxp,imx-gpio"; |
| reg = <0x30200000 DT_SIZE_K(64)>; |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 65 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0", "irq_1"; |
| interrupt-parent = <&gic>; |
| rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <30>; |
| status = "disabled"; |
| }; |
| |
| gpio2: gpio@30210000 { |
| compatible = "nxp,imx-gpio"; |
| reg = <0x30210000 DT_SIZE_K(64)>; |
| interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 67 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0", "irq_1"; |
| interrupt-parent = <&gic>; |
| rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <21>; |
| status = "disabled"; |
| }; |
| |
| gpio3: gpio@30220000 { |
| compatible = "nxp,imx-gpio"; |
| reg = <0x30220000 DT_SIZE_K(64)>; |
| interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 69 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0", "irq_1"; |
| interrupt-parent = <&gic>; |
| rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <26>; |
| status = "disabled"; |
| }; |
| |
| gpio4: gpio@30230000 { |
| compatible = "nxp,imx-gpio"; |
| reg = <0x30230000 DT_SIZE_K(64)>; |
| interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 71 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0", "irq_1"; |
| interrupt-parent = <&gic>; |
| rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <32>; |
| gpio-reserved-ranges = <0 21>; |
| status = "disabled"; |
| }; |
| |
| gpio5: gpio@30240000 { |
| compatible = "nxp,imx-gpio"; |
| reg = <0x30240000 DT_SIZE_K(64)>; |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 73 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0", "irq_1"; |
| interrupt-parent = <&gic>; |
| rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| ngpios = <30>; |
| status = "disabled"; |
| }; |
| |
| gpt1: gpt@302d0000 { |
| compatible = "nxp,imx-gpt"; |
| reg = <0x302d0000 DT_SIZE_K(64)>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| gptfreq = <24000000>; |
| clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x6C 20>; |
| status = "disabled"; |
| }; |
| |
| gpt2: gpt@302e0000 { |
| compatible = "nxp,imx-gpt"; |
| reg = <0x302e0000 DT_SIZE_K(64)>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| gptfreq = <24000000>; |
| clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x68 24>; |
| status = "disabled"; |
| }; |
| |
| iomuxc: iomuxc@30330000 { |
| compatible = "nxp,imx-iomuxc"; |
| reg = <0x30330000 DT_SIZE_K(64)>; |
| status = "okay"; |
| pinctrl: pinctrl { |
| status = "okay"; |
| compatible = "nxp,imx8mp-pinctrl"; |
| }; |
| }; |
| |
| ana_pll: ana_pll@30360000 { |
| compatible = "nxp,imx-ana"; |
| reg = <0x30360000 DT_SIZE_K(64)>; |
| }; |
| |
| ccm: ccm@30380000 { |
| compatible = "nxp,imx-ccm"; |
| reg = <0x30380000 DT_SIZE_K(64)>; |
| #clock-cells = <3>; |
| }; |
| |
| uart2: serial@30890000 { |
| compatible = "nxp,imx-iuart"; |
| reg = <0x30890000 DT_SIZE_K(64)>; |
| interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0"; |
| interrupt-parent = <&gic>; |
| clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>; |
| rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ |
| RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@30a60000 { |
| compatible = "nxp,imx-iuart"; |
| reg = <0x30a60000 DT_SIZE_K(64)>; |
| interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0"; |
| interrupt-parent = <&gic>; |
| clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; |
| rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ |
| RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@30a20000 { |
| compatible = "nxp,ii2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x30a20000 0x10000>; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&gic>; |
| clocks = <&ccm IMX_CCM_I2C1_CLK 0 0>; |
| rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@30a30000 { |
| compatible = "nxp,ii2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x30a30000 0x10000>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&gic>; |
| clocks = <&ccm IMX_CCM_I2C2_CLK 0 0>; |
| rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@30a40000 { |
| compatible = "nxp,ii2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x30a40000 0x10000>; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&gic>; |
| clocks = <&ccm IMX_CCM_I2C3_CLK 0 0>; |
| rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@30a50000 { |
| compatible = "nxp,ii2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x30a50000 0x10000>; |
| interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&gic>; |
| clocks = <&ccm IMX_CCM_I2C4_CLK 0 0>; |
| rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>; |
| status = "disabled"; |
| }; |
| |
| rdc: rdc@303d0000 { |
| compatible = "nxp,rdc"; |
| reg = <0x303d0000 DT_SIZE_K(64)>; |
| }; |
| |
| enet: enet@30be0000 { |
| compatible = "nxp,enet1g"; |
| reg = <0x30be0000 DT_SIZE_K(64)>; |
| clocks = <&ccm IMX_CCM_ENET_CLK 0 0>; |
| rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>; |
| status = "disabled"; |
| |
| enet_mac: ethernet { |
| compatible = "nxp,enet-mac"; |
| interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "COMMON"; |
| interrupt-parent = <&gic>; |
| nxp,mdio = <&enet_mdio>; |
| nxp,ptp-clock = <&enet_ptp_clock>; |
| status = "disabled"; |
| }; |
| enet_mdio: mdio { |
| compatible = "nxp,enet-mdio"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| enet_ptp_clock: ptp_clock { |
| compatible = "nxp,enet-ptp-clock"; |
| interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&gic>; |
| clocks = <&ccm IMX_CCM_ENET_PLL 0 0>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| /* |
| * GPIO pinmux options. These options define the pinmux settings |
| * for GPIO ports on the package, so that the GPIO driver can |
| * select GPIO mux options during GPIO configuration. |
| */ |
| |
| &gpio1{ |
| pinmux = <&iomuxc_gpio1_io00_gpio_io_gpio1_io0>, |
| <&iomuxc_gpio1_io01_gpio_io_gpio1_io1>, |
| <&iomuxc_gpio1_io02_gpio_io_gpio1_io2>, |
| <&iomuxc_gpio1_io03_gpio_io_gpio1_io3>, |
| <&iomuxc_gpio1_io04_gpio_io_gpio1_io4>, |
| <&iomuxc_gpio1_io05_gpio_io_gpio1_io5>, |
| <&iomuxc_gpio1_io06_gpio_io_gpio1_io6>, |
| <&iomuxc_gpio1_io07_gpio_io_gpio1_io7>, |
| <&iomuxc_gpio1_io08_gpio_io_gpio1_io8>, |
| <&iomuxc_gpio1_io09_gpio_io_gpio1_io9>, |
| <&iomuxc_gpio1_io10_gpio_io_gpio1_io10>, |
| <&iomuxc_gpio1_io11_gpio_io_gpio1_io11>, |
| <&iomuxc_gpio1_io12_gpio_io_gpio1_io12>, |
| <&iomuxc_gpio1_io13_gpio_io_gpio1_io13>, |
| <&iomuxc_gpio1_io14_gpio_io_gpio1_io14>, |
| <&iomuxc_gpio1_io15_gpio_io_gpio1_io15>, |
| <&iomuxc_enet_mdc_gpio_io_gpio1_io16>, |
| <&iomuxc_enet_mdio_gpio_io_gpio1_io17>, |
| <&iomuxc_enet_td3_gpio_io_gpio1_io18>, |
| <&iomuxc_enet_td2_gpio_io_gpio1_io19>, |
| <&iomuxc_enet_td1_gpio_io_gpio1_io20>, |
| <&iomuxc_enet_td0_gpio_io_gpio1_io21>, |
| <&iomuxc_enet_tx_ctl_gpio_io_gpio1_io22>, |
| <&iomuxc_enet_txc_gpio_io_gpio1_io23>, |
| <&iomuxc_enet_rx_ctl_gpio_io_gpio1_io24>, |
| <&iomuxc_enet_rxc_gpio_io_gpio1_io25>, |
| <&iomuxc_enet_rd0_gpio_io_gpio1_io26>, |
| <&iomuxc_enet_rd1_gpio_io_gpio1_io27>, |
| <&iomuxc_enet_rd2_gpio_io_gpio1_io28>, |
| <&iomuxc_enet_rd3_gpio_io_gpio1_io29>; |
| }; |
| |
| &gpio2{ |
| pinmux = <&iomuxc_sd1_clk_gpio_io_gpio2_io0>, |
| <&iomuxc_sd1_cmd_gpio_io_gpio2_io1>, |
| <&iomuxc_sd1_data0_gpio_io_gpio2_io2>, |
| <&iomuxc_sd1_data1_gpio_io_gpio2_io3>, |
| <&iomuxc_sd1_data2_gpio_io_gpio2_io4>, |
| <&iomuxc_sd1_data3_gpio_io_gpio2_io5>, |
| <&iomuxc_sd1_data4_gpio_io_gpio2_io6>, |
| <&iomuxc_sd1_data5_gpio_io_gpio2_io7>, |
| <&iomuxc_sd1_data6_gpio_io_gpio2_io8>, |
| <&iomuxc_sd1_data7_gpio_io_gpio2_io9>, |
| <&iomuxc_sd1_reset_b_gpio_io_gpio2_io10>, |
| <&iomuxc_sd1_strobe_gpio_io_gpio2_io11>, |
| <&iomuxc_sd2_cd_b_gpio_io_gpio2_io12>, |
| <&iomuxc_sd2_clk_gpio_io_gpio2_io13>, |
| <&iomuxc_sd2_cmd_gpio_io_gpio2_io14>, |
| <&iomuxc_sd2_data0_gpio_io_gpio2_io15>, |
| <&iomuxc_sd2_data1_gpio_io_gpio2_io16>, |
| <&iomuxc_sd2_data2_gpio_io_gpio2_io17>, |
| <&iomuxc_sd2_data3_gpio_io_gpio2_io18>, |
| <&iomuxc_sd2_reset_b_gpio_io_gpio2_io19>, |
| <&iomuxc_sd2_wp_gpio_io_gpio2_io20>; |
| }; |
| |
| &gpio3{ |
| pinmux = <&iomuxc_nand_ale_gpio_io_gpio3_io0>, |
| <&iomuxc_nand_ce0_b_gpio_io_gpio3_io1>, |
| <&iomuxc_nand_ce1_b_gpio_io_gpio3_io2>, |
| <&iomuxc_nand_ce2_b_gpio_io_gpio3_io3>, |
| <&iomuxc_nand_ce3_b_gpio_io_gpio3_io4>, |
| <&iomuxc_nand_cle_gpio_io_gpio3_io5>, |
| <&iomuxc_nand_data00_gpio_io_gpio3_io6>, |
| <&iomuxc_nand_data01_gpio_io_gpio3_io7>, |
| <&iomuxc_nand_data02_gpio_io_gpio3_io8>, |
| <&iomuxc_nand_data03_gpio_io_gpio3_io9>, |
| <&iomuxc_nand_data04_gpio_io_gpio3_io10>, |
| <&iomuxc_nand_data05_gpio_io_gpio3_io11>, |
| <&iomuxc_nand_data06_gpio_io_gpio3_io12>, |
| <&iomuxc_nand_data07_gpio_io_gpio3_io13>, |
| <&iomuxc_nand_dqs_gpio_io_gpio3_io14>, |
| <&iomuxc_nand_re_b_gpio_io_gpio3_io15>, |
| <&iomuxc_nand_ready_b_gpio_io_gpio3_io16>, |
| <&iomuxc_nand_we_b_gpio_io_gpio3_io17>, |
| <&iomuxc_nand_wp_b_gpio_io_gpio3_io18>, |
| <&iomuxc_sai5_rxfs_gpio_io_gpio3_io19>, |
| <&iomuxc_sai5_rxc_gpio_io_gpio3_io20>, |
| <&iomuxc_sai5_rxd0_gpio_io_gpio3_io21>, |
| <&iomuxc_sai5_rxd1_gpio_io_gpio3_io22>, |
| <&iomuxc_sai5_rxd2_gpio_io_gpio3_io23>, |
| <&iomuxc_sai5_rxd3_gpio_io_gpio3_io24>, |
| <&iomuxc_sai5_mclk_gpio_io_gpio3_io25>; |
| }; |
| |
| /* |
| * Use the NULL pinmux for the GPIO io port which is not available to |
| * make the driver to be easy. |
| */ |
| &iomuxc { |
| /omit-if-no-ref/ null_pinmux: NULL_PINMUX { |
| pinmux = <0x0 0 0x0 0 0x0>; |
| }; |
| }; |
| |
| &gpio4{ |
| pinmux = <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&null_pinmux>, |
| <&iomuxc_sai2_rxfs_gpio_io_gpio4_io21>, |
| <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>, |
| <&iomuxc_sai2_rxd0_gpio_io_gpio4_io23>, |
| <&iomuxc_sai2_txfs_gpio_io_gpio4_io24>, |
| <&iomuxc_sai2_txc_gpio_io_gpio4_io25>, |
| <&iomuxc_sai2_txd0_gpio_io_gpio4_io26>, |
| <&iomuxc_sai2_mclk_gpio_io_gpio4_io27>, |
| <&iomuxc_sai3_rxfs_gpio_io_gpio4_io28>, |
| <&iomuxc_sai3_rxc_gpio_io_gpio4_io29>, |
| <&iomuxc_sai3_rxd_gpio_io_gpio4_io30>, |
| <&iomuxc_sai3_txfs_gpio_io_gpio4_io31>; |
| }; |
| |
| &gpio5{ |
| pinmux = <&iomuxc_sai3_txc_gpio_io_gpio5_io0>, |
| <&iomuxc_sai3_txd_gpio_io_gpio5_io1>, |
| <&iomuxc_sai3_mclk_gpio_io_gpio5_io2>, |
| <&iomuxc_spdif_tx_gpio_io_gpio5_io3>, |
| <&iomuxc_spdif_rx_gpio_io_gpio5_io4>, |
| <&iomuxc_spdif_ext_clk_gpio_io_gpio5_io5>, |
| <&iomuxc_ecspi1_sclk_gpio_io_gpio5_io6>, |
| <&iomuxc_ecspi1_mosi_gpio_io_gpio5_io7>, |
| <&iomuxc_ecspi1_miso_gpio_io_gpio5_io8>, |
| <&iomuxc_ecspi1_ss0_gpio_io_gpio5_io9>, |
| <&iomuxc_ecspi2_sclk_gpio_io_gpio5_io10>, |
| <&iomuxc_ecspi2_mosi_gpio_io_gpio5_io11>, |
| <&iomuxc_ecspi2_miso_gpio_io_gpio5_io12>, |
| <&iomuxc_ecspi2_ss0_gpio_io_gpio5_io13>, |
| <&iomuxc_i2c1_scl_gpio_io_gpio5_io14>, |
| <&iomuxc_i2c1_sda_gpio_io_gpio5_io15>, |
| <&iomuxc_i2c2_scl_gpio_io_gpio5_io16>, |
| <&iomuxc_i2c2_sda_gpio_io_gpio5_io17>, |
| <&iomuxc_i2c3_scl_gpio_io_gpio5_io18>, |
| <&iomuxc_i2c3_sda_gpio_io_gpio5_io19>, |
| <&iomuxc_i2c4_scl_gpio_io_gpio5_io20>, |
| <&iomuxc_i2c4_sda_gpio_io_gpio5_io21>, |
| <&iomuxc_uart1_rxd_gpio_io_gpio5_io22>, |
| <&iomuxc_uart1_txd_gpio_io_gpio5_io23>, |
| <&iomuxc_uart2_rxd_gpio_io_gpio5_io24>, |
| <&iomuxc_uart2_txd_gpio_io_gpio5_io25>, |
| <&iomuxc_uart3_rxd_gpio_io_gpio5_io26>, |
| <&iomuxc_uart3_txd_gpio_io_gpio5_io27>, |
| <&iomuxc_uart4_rxd_gpio_io_gpio5_io28>, |
| <&iomuxc_uart4_txd_gpio_io_gpio5_io29>; |
| }; |
