blob: af9fc0f597151d6afedc11901c5e61fce551fbfb [file] [log] [blame]
CONFIG_ARM=y
CONFIG_BOARD_STM32_MIN_DEV=y
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32F1X=y
CONFIG_SOC_STM32F103X8=y
CONFIG_CORTEX_M_SYSTICK=y
# 72MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
# enable uart driver
CONFIG_SERIAL=y
CONFIG_UART_STM32=y
# enable USART1
CONFIG_UART_STM32_PORT_1=y
# enable console on this port by default
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable pinmux
CONFIG_PINMUX=y
CONFIG_PINMUX_STM32=y
# enable GPIO ports A, B
CONFIG_GPIO=y
CONFIG_GPIO_STM32=y
CONFIG_GPIO_STM32_PORTA=y
CONFIG_GPIO_STM32_PORTB=y
CONFIG_GPIO_STM32_PORTC=n
CONFIG_GPIO_STM32_PORTD=n
# clock configuration
CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# use HSE as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# produce 72MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_XTPRE=n
CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
# APB1 clock must not exceed 36MHz limit
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=0