blob: bb5ac014044500435f61c9cfad36bde1f8bc0c9f [file] [log] [blame]
/*
* Copyright (c) 2018, Diego Sueiro <diego.sueiro@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <init.h>
#include "device_imx.h"
static int colibri_imx7d_m4_pinmux_init(struct device *dev)
{
ARG_UNUSED(dev);
#ifdef CONFIG_GPIO_IMX_PORT_1
/* GPIO1_IO02 Mux Config */
IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02 = 0;
IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02 = 0;
#endif /* CONFIG_GPIO_IMX_PORT_1 */
#ifdef CONFIG_GPIO_IMX_PORT_2
/* GPIO2_IO26 Mux Config */
IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL = 5;
IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL =
IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PS(2) |
IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_HYS_MASK;
#endif /* CONFIG_GPIO_IMX_PORT_2 */
#ifdef CONFIG_UART_IMX_UART_2
IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA =
IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_MUX_MODE(0);
IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA =
IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_MUX_MODE(0);
IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA =
IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_HYS_MASK |
IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_DSE(0);
IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA =
IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_HYS_MASK |
IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_DSE(0);
/* Select TX_PAD for RX data (DTE mode...) */
IOMUXC_UART2_RX_DATA_SELECT_INPUT =
IOMUXC_UART2_RX_DATA_SELECT_INPUT_DAISY(3);
#endif /* CONFIG_UART_IMX_UART_2 */
return 0;
}
SYS_INIT(colibri_imx7d_m4_pinmux_init, PRE_KERNEL_1, 0);