| /* |
| * Copyright (c) 2025 Renesas Electronics Corporation |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/gpio/arducam-ffc-40pin-connector.h> |
| #include <dt-bindings/input/input-event-codes.h> |
| #include "ek_ra8p1-pinctrl.dtsi" |
| #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> |
| #include <zephyr/dt-bindings/memory-controller/renesas,ra-sdram.h> |
| |
| / { |
| leds { |
| compatible = "gpio-leds"; |
| |
| led1: led1 { |
| gpios = <&ioport6 0 GPIO_ACTIVE_HIGH>; |
| label = "LED1"; |
| }; |
| |
| led2: led2 { |
| gpios = <&ioport3 3 GPIO_ACTIVE_HIGH>; |
| label = "LED2"; |
| }; |
| |
| led3: led3 { |
| gpios = <&ioporta 7 GPIO_ACTIVE_HIGH>; |
| label = "LED3"; |
| }; |
| }; |
| |
| buttons { |
| compatible = "gpio-keys"; |
| |
| button0: s1 { |
| gpios = <&ioport0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; |
| label = "Push button switch 1"; |
| zephyr,code = <INPUT_KEY_0>; |
| status = "disabled"; |
| }; |
| |
| button1: s2 { |
| gpios = <&ioport0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; |
| label = "Push button switch 2"; |
| zephyr,code = <INPUT_KEY_1>; |
| status = "disabled"; |
| }; |
| }; |
| |
| sdram1: sdram@68000000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| device_type = "memory"; |
| reg = <0x68000000 DT_SIZE_M(64)>; |
| zephyr,memory-region = "SDRAM"; |
| status = "okay"; |
| }; |
| |
| arducam_ffc_40pin_connector: arducam-ffc-40pin-connector { |
| compatible = "arducam,ffc-40pin-connector"; |
| #gpio-cells = <2>; |
| gpio-map-mask = <0xffffffff 0xffffffc0>; |
| gpio-map-pass-thru = <0x0 0x3f>; |
| gpio-map = <ARDUCAM_FFC_40PIN_RESET 0 &ioport7 9 0>; |
| }; |
| }; |
| |
| &xtal { |
| clock-frequency = <DT_FREQ_M(24)>; |
| mosel = <0>; |
| #clock-cells = <0>; |
| status = "okay"; |
| }; |
| |
| &pll { |
| status = "okay"; |
| |
| pllp: pllp { |
| status = "okay"; |
| }; |
| |
| pllq: pllq { |
| status = "okay"; |
| }; |
| |
| pllr: pllr { |
| status = "okay"; |
| }; |
| }; |
| |
| &pll2 { |
| clocks = <&xtal>; |
| div = <3>; |
| mul = <300 0>; |
| status = "okay"; |
| |
| pll2p { |
| div = <4>; |
| freq = <DT_FREQ_M(600)>; |
| status = "okay"; |
| }; |
| |
| pll2q { |
| div = <3>; |
| freq = <DT_FREQ_M(800)>; |
| status = "okay"; |
| }; |
| |
| pll2r { |
| div = <5>; |
| freq = <DT_FREQ_M(480)>; |
| status = "okay"; |
| }; |
| }; |
| |
| &sciclk { |
| clocks = <&pll2r>; |
| div = <4>; |
| status = "okay"; |
| }; |
| |
| &lcdclk { |
| clocks = <&pll2r>; |
| div = <2>; |
| status = "okay"; |
| }; |
| |
| &uclk { |
| clocks = <&pll2r>; |
| div = <10>; |
| status = "okay"; |
| }; |
| |
| &gptclk { |
| clocks = <&pll2p>; |
| div = <2>; |
| status = "okay"; |
| }; |
| |
| &ioport0 { |
| status = "okay"; |
| }; |
| |
| &ioport1 { |
| status = "okay"; |
| }; |
| |
| &ioport2 { |
| status = "okay"; |
| }; |
| |
| &ioport3 { |
| status = "okay"; |
| }; |
| |
| &ioport4 { |
| status = "okay"; |
| }; |
| |
| &ioport5 { |
| status = "okay"; |
| }; |
| |
| &ioport6 { |
| status = "okay"; |
| }; |
| |
| &ioport7 { |
| status = "okay"; |
| }; |
| |
| &ioport8 { |
| status = "okay"; |
| }; |
| |
| &ioporta { |
| status = "okay"; |
| }; |
| |
| &usbfs { |
| pinctrl-0 = <&usbfs_default>; |
| pinctrl-names = "default"; |
| maximum-speed = "full-speed"; |
| }; |
| |
| &usbhs { |
| pinctrl-0 = <&usbhs_default>; |
| pinctrl-names = "default"; |
| maximum-speed = "high-speed"; |
| }; |
| |
| &usbhs_phy { |
| phys-clock-src = "xtal"; |
| }; |
| |
| &sdram { |
| pinctrl-0 = <&sdram_default>; |
| pinctrl-names = "default"; |
| status = "okay"; |
| auto-refresh-interval = <SDRAM_AUTO_REFREDSH_INTERVEL_10CYCLES>; |
| auto-refresh-count = <SDRAM_AUTO_REFREDSH_COUNT_8TIMES>; |
| precharge-cycle-count = <SDRAM_AUTO_PRECHARGE_CYCLE_3CYCLES>; |
| multiplex-addr-shift = "9-bit"; |
| edian-mode = "little-endian"; |
| continuous-access; |
| bus-width = "32-bit"; |
| |
| bank@0 { |
| reg = <0>; |
| renesas,ra-sdram-timing = <SDRAM_TRAS_6CYCLES |
| SDRAM_TRCD_3CYCLES |
| SDRAM_TRP_3CYCLES |
| SDRAM_TWR_2CYCLES |
| SDRAM_TCL_3CYCLES |
| 937 |
| SDRAM_TREFW_8CYCLES>; |
| }; |
| }; |