dts/arm64/rockchip/rk3399.dtsi

/*
 * Copyright 2022 Huawei France Technologies SASU
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arm64/armv8-a.dtsi>
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
#include <mem.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x3>;
		};
		cpu@4 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0 0x100>;
		};
		cpu@5 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0 0x101>;
		};
	};

	gic: interrupt-controller@fee00000  {
		#address-cells = <1>;
		compatible = "arm,gic";
		reg = <0xfee00000 0x10000>, /* GICD */
		      <0xfef00000 0xc0000>, /* GICR */
		      <0xfff00000 0x10000>, /* GICC */
		      <0xfff10000 0x10000>, /* GICH */
		      <0xfff20000 0x10000>; /* GICV */
		interrupt-controller;
		#interrupt-cells = <4>;
		status = "okay";
	};

	psci: psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	sram0: memory@10000000 {
		reg = <0x10000000 DT_SIZE_M(128)>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>;
	};

	uart2: serial@ff1a0000  {
		compatible = "rockchip,rk3399-uart", "ns16550";
		reg = <0xff1a0000 0x1000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		status = "disabled";
		reg-shift = <2>;
		clock-frequency = <350000000>;
	};
};