| /* |
| * Copyright (c) 2018 Yurii Hamann |
| * Copyright (c) 2019 Centaur Analytics, Inc |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv7-m.dtsi> |
| #include <zephyr/dt-bindings/clock/stm32f7_clock.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/pwm/pwm.h> |
| #include <zephyr/dt-bindings/pwm/stm32_pwm.h> |
| #include <zephyr/dt-bindings/dma/stm32_dma.h> |
| #include <zephyr/dt-bindings/adc/stm32f4_adc.h> |
| #include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h> |
| #include <zephyr/dt-bindings/adc/adc.h> |
| #include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h> |
| #include <freq.h> |
| |
| / { |
| chosen { |
| zephyr,entropy = &rng; |
| zephyr,flash-controller = &flash; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m7"; |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| mpu: mpu@e000ed90 { |
| compatible = "arm,armv7m-mpu"; |
| reg = <0xe000ed90 0x40>; |
| arm,num-mpu-regions = <8>; |
| }; |
| }; |
| }; |
| |
| quadspi_memory: memory@90000000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| reg = <0x90000000 DT_SIZE_M(256)>; |
| zephyr,memory-region = "QSPI"; |
| zephyr,memory-region-mpu = "EXTMEM"; |
| }; |
| |
| clocks { |
| clk_hse: clk-hse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-hse-clock"; |
| status = "disabled"; |
| }; |
| |
| clk_hsi: clk-hsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(16)>; |
| status = "disabled"; |
| }; |
| |
| clk_lse: clk-lse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-lse-clock"; |
| clock-frequency = <32768>; |
| driving-capability = <0>; |
| status = "disabled"; |
| }; |
| |
| clk_lsi: clk-lsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_K(32)>; |
| status = "disabled"; |
| }; |
| |
| pll: pll { |
| #clock-cells = <0>; |
| compatible = "st,stm32f7-pll-clock"; |
| status = "disabled"; |
| }; |
| }; |
| |
| soc { |
| fmc: memory-controller@a0000000 { |
| compatible = "st,stm32-fmc"; |
| reg = <0xa0000000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>; |
| status = "disabled"; |
| |
| sdram: sdram { |
| compatible = "st,stm32-fmc-sdram"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| flash: flash-controller@40023c00 { |
| compatible = "st,stm32-flash-controller", "st,stm32f7-flash-controller"; |
| reg = <0x40023c00 0x400>; |
| interrupts = <4 0>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "st,stm32-nv-flash", "soc-nv-flash"; |
| |
| write-block-size = <1>; |
| /* maximum erase time (ms) for a 256K sector */ |
| max-erase-time = <4000>; |
| }; |
| }; |
| |
| rcc: rcc@40023800 { |
| compatible = "st,stm32-rcc"; |
| #clock-cells = <2>; |
| reg = <0x40023800 0x400>; |
| |
| rctl: reset-controller { |
| compatible = "st,stm32-rcc-rctl"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| exti: interrupt-controller@40013c00 { |
| compatible = "st,stm32-exti"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| #address-cells = <1>; |
| reg = <0x40013c00 0x400>; |
| num-lines = <16>; |
| interrupts = <6 0>, <7 0>, <8 0>, <9 0>, |
| <10 0>, <23 0>, <40 0>; |
| interrupt-names = "line0", "line1", "line2", "line3", |
| "line4", "line5-9", "line10-15"; |
| line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, |
| <4 1>, <5 5>, <10 6>; |
| }; |
| |
| pinctrl: pin-controller@40020000 { |
| compatible = "st,stm32-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x40020000 0x2400>; |
| |
| gpioa: gpio@40020000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40020000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>; |
| }; |
| |
| gpiob: gpio@40020400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40020400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>; |
| }; |
| |
| gpioc: gpio@40020800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40020800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>; |
| }; |
| |
| gpiod: gpio@40020C00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40020C00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>; |
| }; |
| |
| gpioe: gpio@40021000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40021000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>; |
| }; |
| |
| gpiof: gpio@40021400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40021400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>; |
| }; |
| |
| gpiog: gpio@40021800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40021800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>; |
| }; |
| |
| gpioh: gpio@40021C00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40021C00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>; |
| }; |
| |
| gpioi: gpio@40022000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40022000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>; |
| }; |
| }; |
| |
| iwdg: watchdog@40003000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x40003000 0x400>; |
| status = "disabled"; |
| }; |
| |
| wwdg: watchdog@40002c00 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x40002C00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; |
| interrupts = <0 7>; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@40011000 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40011000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>; |
| resets = <&rctl STM32_RESET(APB2, 4U)>; |
| interrupts = <37 0>; |
| status = "disabled"; |
| }; |
| |
| usart2: serial@40004400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; |
| resets = <&rctl STM32_RESET(APB1, 17U)>; |
| interrupts = <38 0>; |
| status = "disabled"; |
| }; |
| |
| usart3: serial@40004800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; |
| resets = <&rctl STM32_RESET(APB1, 18U)>; |
| interrupts = <39 0>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@40004c00 { |
| compatible ="st,stm32-uart"; |
| reg = <0x40004c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; |
| resets = <&rctl STM32_RESET(APB1, 19U)>; |
| interrupts = <52 0>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@40005000 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40005000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>; |
| resets = <&rctl STM32_RESET(APB1, 20U)>; |
| interrupts = <53 0>; |
| status = "disabled"; |
| }; |
| |
| usart6: serial@40011400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40011400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>; |
| resets = <&rctl STM32_RESET(APB2, 5U)>; |
| interrupts = <71 0>; |
| status = "disabled"; |
| }; |
| |
| uart7: serial@40007800 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40007800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>; |
| resets = <&rctl STM32_RESET(APB1, 30U)>; |
| interrupts = <82 0>; |
| status = "disabled"; |
| }; |
| |
| uart8: serial@40007c00 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40007c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>; |
| resets = <&rctl STM32_RESET(APB1, 31U)>; |
| interrupts = <83 0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>; |
| interrupts = <31 0>, <32 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@40005800 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; |
| interrupts = <33 0>, <34 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@40005c00 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>; |
| interrupts = <72 0>, <73 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@40013000 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>; |
| interrupts = <35 5>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@40003800 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; |
| interrupts = <36 5>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@40003c00 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>; |
| interrupts = <51 5>; |
| status = "disabled"; |
| }; |
| |
| spi4: spi@40013400 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>; |
| interrupts = <84 5>; |
| status = "disabled"; |
| }; |
| |
| spi5: spi@40015000 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40015000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>; |
| interrupts = <85 5>; |
| status = "disabled"; |
| }; |
| |
| can1: can@40006400 { |
| compatible = "st,stm32-can"; |
| reg = <0x40006400 0x400>; |
| interrupts = <19 0>, <20 0>, <21 0>, <22 0>; |
| interrupt-names = "TX", "RX0", "RX1", "SCE"; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; |
| status = "disabled"; |
| sjw = <1>; |
| sample-point = <875>; |
| }; |
| |
| timers1: timers@40010000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40010000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>; |
| resets = <&rctl STM32_RESET(APB2, 0U)>; |
| interrupts = <24 0>, <25 0>, <26 0>, <27 0>; |
| interrupt-names = "brk", "up", "trgcom", "cc"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers2: timers@40000000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>; |
| resets = <&rctl STM32_RESET(APB1, 0U)>; |
| interrupts = <28 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers3: timers@40000400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; |
| resets = <&rctl STM32_RESET(APB1, 1U)>; |
| interrupts = <29 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers4: timers@40000800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>; |
| resets = <&rctl STM32_RESET(APB1, 2U)>; |
| interrupts = <30 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers5: timers@40000c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>; |
| resets = <&rctl STM32_RESET(APB1, 3U)>; |
| interrupts = <50 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers6: timers@40001000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>; |
| resets = <&rctl STM32_RESET(APB1, 4U)>; |
| interrupts = <54 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers7: timers@40001400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>; |
| resets = <&rctl STM32_RESET(APB1, 5U)>; |
| interrupts = <55 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers8: timers@40010400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40010400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>; |
| resets = <&rctl STM32_RESET(APB2, 1U)>; |
| interrupts = <43 0>, <44 0>, <45 0>, <46 0>; |
| interrupt-names = "brk", "up", "trgcom", "cc"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers9: timers@40014000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>; |
| resets = <&rctl STM32_RESET(APB2, 16U)>; |
| interrupts = <24 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers10: timers@40014400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>; |
| resets = <&rctl STM32_RESET(APB2, 17U)>; |
| interrupts = <25 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers11: timers@40014800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>; |
| resets = <&rctl STM32_RESET(APB2, 18U)>; |
| interrupts = <26 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers12: timers@40001800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>; |
| resets = <&rctl STM32_RESET(APB1, 6U)>; |
| interrupts = <43 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers13: timers@40001c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>; |
| resets = <&rctl STM32_RESET(APB1, 7U)>; |
| interrupts = <44 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers14: timers@40002000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40002000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>; |
| resets = <&rctl STM32_RESET(APB1, 8U)>; |
| interrupts = <45 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| usbotg_fs: usb@50000000 { |
| compatible = "st,stm32-otgfs"; |
| reg = <0x50000000 0x40000>; |
| interrupts = <67 0>; |
| interrupt-names = "otgfs"; |
| num-bidir-endpoints = <6>; |
| ram-size = <1280>; |
| maximum-speed = "full-speed"; |
| phys = <&otgfs_phy>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>, |
| <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>; |
| status = "disabled"; |
| }; |
| |
| usbotg_hs: usb@40040000 { |
| compatible = "st,stm32-otghs"; |
| reg = <0x40040000 0x40000>; |
| interrupts = <77 0>, <74 0>, <75 0>; |
| interrupt-names = "otghs", "ep1_out", "ep1_in"; |
| num-bidir-endpoints = <9>; |
| ram-size = <4096>; |
| maximum-speed = "full-speed"; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>; |
| phys = <&otghs_fs_phy>; |
| status = "disabled"; |
| }; |
| |
| rtc: rtc@40002800 { |
| compatible = "st,stm32-rtc"; |
| reg = <0x40002800 0x300>; |
| interrupts = <41 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>; |
| prescaler = <32768>; |
| status = "disabled"; |
| |
| bbram: backup_regs { |
| compatible = "st,stm32-bbram"; |
| st,backup-regs = <32>; |
| status = "disabled"; |
| }; |
| }; |
| |
| adc1: adc@40012000 { |
| compatible = "st,stm32f4-adc", "st,stm32-adc"; |
| reg = <0x40012000 0x50>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>; |
| interrupts = <18 0>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| /* Temperature and VBAT sensor share channel 18 */ |
| temp-channel = <18>; |
| vbat-channel = <18>; |
| vref-channel = <17>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x02) |
| STM32_ADC_RES(6, 0x03)>; |
| sampling-times = <3 15 28 56 84 112 144 480>; |
| }; |
| |
| adc2: adc@40012100 { |
| compatible = "st,stm32f4-adc", "st,stm32-adc"; |
| reg = <0x40012100 0x50>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>; |
| interrupts = <18 0>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x02) |
| STM32_ADC_RES(6, 0x03)>; |
| sampling-times = <3 15 28 56 84 112 144 480>; |
| }; |
| |
| adc3: adc@40012200 { |
| compatible = "st,stm32f4-adc", "st,stm32-adc"; |
| reg = <0x40012200 0x50>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>; |
| interrupts = <18 0>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x02) |
| STM32_ADC_RES(6, 0x03)>; |
| sampling-times = <3 15 28 56 84 112 144 480>; |
| }; |
| |
| dac1: dac@40007400 { |
| compatible = "st,stm32-dac"; |
| reg = <0x40007400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| }; |
| |
| dma1: dma@40026000 { |
| compatible = "st,stm32-dma-v1"; |
| #dma-cells = <4>; |
| reg = <0x40026000 0x400>; |
| interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>; |
| status = "disabled"; |
| }; |
| |
| dma2: dma@40026400 { |
| compatible = "st,stm32-dma-v1"; |
| #dma-cells = <4>; |
| reg = <0x40026400 0x400>; |
| interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>; |
| st,mem2mem; |
| status = "disabled"; |
| }; |
| |
| rng: rng@50060800 { |
| compatible = "st,stm32-rng"; |
| reg = <0x50060800 0x400>; |
| interrupts = <80 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>, |
| <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>; |
| status = "disabled"; |
| }; |
| |
| sdmmc1: sdmmc@40012c00 { |
| compatible = "st,stm32-sdmmc"; |
| reg = <0x40012c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>, |
| <&rcc STM32_SRC_PLL_Q SDMMC1_SEL(0)>; |
| resets = <&rctl STM32_RESET(APB2, 11U)>; |
| interrupts = <49 0>; |
| status = "disabled"; |
| }; |
| |
| backup_sram: memory@40024000 { |
| compatible = "zephyr,memory-region", "st,stm32-backup-sram"; |
| reg = <0x40024000 DT_SIZE_K(4)>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>; |
| zephyr,memory-region = "BACKUP_SRAM"; |
| status = "disabled"; |
| }; |
| |
| quadspi: quadspi@a0001000 { |
| compatible = "st,stm32-qspi"; |
| #address-cells = <0x1>; |
| #size-cells = <0x0>; |
| reg = <0xa0001000 0x34>; |
| interrupts = <92 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x2>; |
| status = "disabled"; |
| }; |
| }; |
| |
| die_temp: dietemp { |
| compatible = "st,stm32-temp-cal"; |
| ts-cal1-addr = <0x1FF0F44C>; |
| ts-cal2-addr = <0x1FF0F44E>; |
| ts-cal1-temp = <30>; |
| ts-cal2-temp = <110>; |
| ts-cal-vrefanalog = <3300>; |
| io-channels = <&adc1 18>; |
| status = "disabled"; |
| }; |
| |
| vref: vref { |
| compatible = "st,stm32-vref"; |
| vrefint-cal-addr = <0x1FFF7A2A>; |
| vrefint-cal-mv = <3300>; |
| io-channels = <&adc1 17>; |
| status = "disabled"; |
| }; |
| |
| vbat: vbat { |
| compatible = "st,stm32-vbat"; |
| ratio = <4>; |
| io-channels = <&adc1 18>; |
| status = "disabled"; |
| }; |
| |
| otghs_fs_phy: otghs_fs_phy { |
| compatible = "usb-nop-xceiv"; |
| #phy-cells = <0>; |
| }; |
| |
| otgfs_phy: otgfs_phy { |
| compatible = "usb-nop-xceiv"; |
| #phy-cells = <0>; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
