| # Copyright (c) 2022 NXP |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| description: | |
| The node has the 'pinctrl' node label set in MCUX SoC's devicetree. These |
| nodes can be autogenerated using the MCUXpresso config tools combined with |
| the imx_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg |
| fields in a group select the pins to be configured, and the remaining |
| devicetree properties set configuration values for those pins |
| for example, here is an group configuring LPUART1 pins: |
| |
| group0 { |
| pinmux = <&iomuxc_uart2_rxd_uart_rx_uart2_rx, |
| &iomuxc_uart2_txd_uart_tx_uart2_tx>; |
| bias-pull-up; |
| slew-rate = "slow"; |
| drive-strength = "x1"; |
| }; |
| |
| This will select UART2_RXD as UART2 rx, and UART2_TXD as UART2 tx. |
| Both pins will be configured with a slow slew rate, and x1 drive |
| strength. |
| Note that the soc level iomuxc dts file can be examined to find the possible |
| pinmux options. Here are the affects of each property on the |
| IOMUXC SW_PAD_CTL register: |
| input-schmitt-enable: HYS=1 |
| drive-open-drain: OD=1 |
| bias-pull-down: PD=0 |
| bias-pull-up: PU |
| slew-rate: FSEL1=<enum_idx> |
| drive-strength: DSE=<enum_idx> |
| input-enable: SION=1 (in SW_MUX_CTL_PAD register) |
| |
| If only required properties are supplied, the pin will have the following |
| configuration: |
| HYS=0, |
| PD=0 |
| PU=0 |
| OD=0, |
| FSEL1=<slew-rate>, |
| DSE=<drive-strength>, |
| SION=0, |
| |
| |
| compatible: "nxp,imx93-pinctrl" |
| |
| include: base.yaml |
| |
| child-binding: |
| description: iMX pin controller pin group |
| child-binding: |
| description: | |
| iMX pin controller pin configuration node. |
| |
| include: |
| - name: pincfg-node.yaml |
| property-allowlist: |
| - input-schmitt-enable |
| - drive-open-drain |
| - input-enable |
| - bias-pull-up |
| - bias-pull-down |
| |
| properties: |
| pinmux: |
| required: true |
| type: phandles |
| description: | |
| Pin mux selections for this group. See the soc level iomuxc DTSI file |
| for a defined list of these options. |
| drive-strength: |
| required: true |
| type: string |
| enum: |
| - "x0" |
| - "x1" |
| - "x2" |
| - "x3" |
| - "x4" |
| - "x5" |
| - "x6" |
| description: | |
| Pin output drive strength. Sets the DSE field in the IOMUXC peripheral. |
| 00_0000 X0, No driver |
| 00_0001 X1 |
| 00_0011 X2 |
| 00_0111 X3 |
| 00_1111 X4 |
| 01_1111 X5 |
| 11_1111 X6 |
| slew-rate: |
| required: true |
| type: string |
| enum: |
| - "slow" |
| - "slightly_slow" |
| - "slightly_fast" |
| - "fast" |
| description: | |
| Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral |
| 0 SLOW — Slow Frequency Slew Rate |
| 1 Slightly SLOW — Slightly Slow Frequency Slew Rate |
| 2 Slightly FAST — Slightly Fast Frequency Slew Rate |
| 3 FAST — Fast Frequency Slew Rate |
