|  | # ARM architecture configuration options | 
|  |  | 
|  | # Copyright (c) 2014-2015 Wind River Systems, Inc. | 
|  | # SPDX-License-Identifier: Apache-2.0 | 
|  |  | 
|  | menu "ARM Options" | 
|  | depends on ARM | 
|  |  | 
|  | config ARCH | 
|  | default "arm" | 
|  |  | 
|  | config CPU_CORTEX | 
|  | bool | 
|  | help | 
|  | This option signifies the use of a CPU of the Cortex family. | 
|  |  | 
|  | config ARM_CUSTOM_INTERRUPT_CONTROLLER | 
|  | bool | 
|  | depends on !CPU_CORTEX_M | 
|  | help | 
|  | This option indicates that the ARM CPU is connected to a custom (i.e. | 
|  | non-GIC) interrupt controller. | 
|  |  | 
|  | A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...) | 
|  | allow interfacing to a custom external interrupt controller and this | 
|  | option must be selected when such cores are connected to an interrupt | 
|  | controller that is not the ARM Generic Interrupt Controller (GIC). | 
|  |  | 
|  | When this option is selected, the architecture interrupt control | 
|  | functions are mapped to the SoC interrupt control interface, which is | 
|  | implemented at the SoC level. | 
|  |  | 
|  | N.B. This option is only applicable to the Cortex-A and Cortex-R | 
|  | family cores. The Cortex-M family cores are always equipped with | 
|  | the ARM Nested Vectored Interrupt Controller (NVIC). | 
|  |  | 
|  | config CODE_DATA_RELOCATION_SRAM | 
|  | bool "Relocate code/data sections to SRAM" | 
|  | depends on CPU_CORTEX_M | 
|  | select CODE_DATA_RELOCATION | 
|  | help | 
|  | When selected this will relocate .text, data and .bss sections from | 
|  | the specified files and places it in SRAM. The files should be specified | 
|  | in the CMakeList.txt file with a cmake API zephyr_code_relocate(). This | 
|  | config is used to create an MPU entry for the SRAM space used for code | 
|  | relocation. | 
|  |  | 
|  | config ARM_ON_ENTER_CPU_IDLE_HOOK | 
|  | bool | 
|  | help | 
|  | Enables a hook (z_arm_on_enter_cpu_idle()) that is called when | 
|  | the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()). | 
|  | If needed, this hook can be used to prevent the CPU from actually | 
|  | entering sleep by skipping the WFE/WFI instruction. | 
|  |  | 
|  | config ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK | 
|  | bool | 
|  | help | 
|  | Enables a hook (z_arm_on_enter_cpu_idle_prepare()) that is called when | 
|  | the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()). | 
|  | If needed, this hook can prepare data to upcoming call to | 
|  | z_arm_on_enter_cpu_idle(). The z_arm_on_enter_cpu_idle_prepare differs | 
|  | from z_arm_on_enter_cpu_idle because it is called before interrupts are | 
|  | disabled. | 
|  |  | 
|  | config ARM_ON_EXIT_CPU_IDLE | 
|  | bool | 
|  | help | 
|  | Enables a possibility to inject SoC-specific code just after WFI/WFE | 
|  | instructions of the cpu idle implementation. | 
|  |  | 
|  | Enabling this option requires that the SoC provides a soc_cpu_idle.h | 
|  | header file which defines SOC_ON_EXIT_CPU_IDLE macro guarded by | 
|  | _ASMLANGUAGE. | 
|  |  | 
|  | The SOC_ON_EXIT_CPU_IDLE macro is expanded just after | 
|  | WFI/WFE instructions before any memory access is performed. The purpose | 
|  | of the SOC_ON_EXIT_CPU_IDLE is to perform an action that mitigate issues | 
|  | observed on some SoCs caused by a memory access following WFI/WFE | 
|  | instructions. | 
|  |  | 
|  | rsource "core/Kconfig" | 
|  | rsource "core/Kconfig.vfp" | 
|  |  | 
|  | endmenu |