tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay

/*
 * Copyright (c) 2022 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* Clocks clean up config
 * Aim is to avoid conflict with specific default board configuration
 */

&clk_hse {
	status = "disabled";
	/delete-property/ hse-bypass;
	/delete-property/ clock-frequency;
};

&clk_hsi {
	status = "disabled";
};

&pll {
	/delete-property/ div-m;
	/delete-property/ mul-n;
	/delete-property/ div-p;
	/delete-property/ div-q;
	/delete-property/ div-r;
	/delete-property/ clocks;
	status = "disabled";
};

&rcc {
	/delete-property/ clocks;
	/delete-property/ clock-frequency;
};


/* Core set up
 * Aim of this part is to provide a base working clock config
 */

&clk_hsi {
	status = "okay";
};

&clk_lse {
	status = "okay";
};

&pll {
	div-m = <1>;
	mul-n = <8>;
	div-p = <20>; /* 6.4 MHz */
	div-q = <2>;
	div-r = <2>;
	clocks = <&clk_hsi>;
	status = "okay";
};

&rcc {
	clocks = <&pll>;
	clock-frequency = <DT_FREQ_M(64)>;
	ahb-prescaler = <1>;
	apb1-prescaler = <2>;
};

&i2c1 {
	/delete-property/ clocks;
	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
			<&rcc STM32_SRC_HSI I2C1_SEL(2)>;
	status = "okay";
};

&lptim1 {
	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
			<&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
	status = "okay";
};

&adc1 {
	clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>,
			<&rcc STM32_SRC_PLL_P ADC_SEL(1)>;
	status = "okay";
};