tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/clear_clocks.overlay

/*
 * Copyright (c) 2021 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Warning: This overlay clears clocks back to a state equivalent to what could
 * be found in stm32h7.dtsi
 */

&clk_hse {
	status = "disabled";
	/delete-property/ hse-bypass;
	/delete-property/ clock-frequency;
};

&clk_hsi {
	status = "disabled";
	/delete-property/ hsi-div;
};

&clk_csi {
	status = "disabled";
};

&clk_lse {
	status = "disabled";
};

&clk_lsi {
	status = "disabled";
};

&pll {
	/delete-property/ div-m;
	/delete-property/ mul-n;
	/delete-property/ div-p;
	/delete-property/ div-q;
	/delete-property/ div-r;
	/delete-property/ clocks;
	status = "disabled";
};

&pll3 {
	/delete-property/ div-m;
	/delete-property/ mul-n;
	/delete-property/ div-p;
	/delete-property/ div-q;
	/delete-property/ div-r;
	/delete-property/ clocks;
	status = "disabled";
};

&rcc {
	/delete-property/ clocks;
	/delete-property/ clock-frequency;
	/delete-property/ d1cpre;
	/delete-property/ hpre;
	/delete-property/ d1ppre;
	/delete-property/ d2ppre1;
	/delete-property/ d2ppre2;
	/delete-property/ d3ppre;
};