tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pllq_2_d1ppre_4.overlay

/*
 * Copyright (c) 2021 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Warning: This overlay performs configuration from clean sheet.
 * It is assumed that it is applied after core_init.overlay file.
 */

/* With this particular div-q and d1ppre values
 * APB2 and PLL_Q clock frequencies are equal.
 * This setting is default stm32h7 SPI devices configuration.
 * This test config ensures it still works.
 */

&pll {
	/delete-property/ div-q;
	div-q = <2>;
};

&rcc {
	/delete-property/ d1ppre;
	d1ppre = <4>;
};

&spi1 {
	/delete-property/ clocks;
	clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
	status = "okay";
};