drivers/espi/Kconfig.npcx

# NPCX eSPI driver configuration options

# Copyright (c) 2020 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0

config ESPI_NPCX
	bool "Nuvoton NPCX embedded controller (EC) ESPI driver"
	default y
	depends on SOC_FAMILY_NPCX
	depends on DT_HAS_NUVOTON_NPCX_ESPI_ENABLED
	select PINCTRL
	help
	  This option enables the Intel Enhanced Serial Peripheral Interface
	  (eSPI) for NPCX family of processors.

config ESPI_NPCX_PERIPHERAL_ACPI_SHD_MEM_SIZE
	int "Host I/O peripheral port size for shared memory in npcx series"
	depends on ESPI_NPCX || ESPI_PERIPHERAL_ACPI_SHM_REGION
	default 256
	help
	  This is the port size used by the Host and EC to communicate over
	  the shared memory region to return the ACPI response data. Please
	  notice the valid value in npcx ec series for this option is 8/16/32/
	  64/128/256/512/1024/2048/4096 bytes.

config ESPI_NPCX_PERIPHERAL_HOST_CMD_PARAM_SIZE
	int "Host I/O peripheral port size for ec host command in npcx series"
	depends on ESPI_NPCX || ESPI_PERIPHERAL_EC_HOST_CMD
	default 256
	help
	  This is the port size used by the Host and EC to communicate over
	  the shared memory region to return the host command parameter data.
	  Please notice the valid value in npcx ec series for this option is
	  8/16/32/64/128/256/512/1024/2048/4096 bytes.

config ESPI_NPCX_BYPASS_CH_ENABLE_FATAL_ERROR
	bool
	depends on SOC_SERIES_NPCX7 || SOC_SERIES_NPCX9
	default y
	help
	  Workaround the issue documented in NPCX99nF errata rev1_2, No.3.10.
	  Enabling an eSPI channel during an eSPI transaction might
	  (with low probability) cause the eSPI_SIF module to transition to
	  a wrong state and therefore response with FATAL_ERROR on an incoming
	  transaction.

config ESPI_NPCX_PERIPHERAL_DEBUG_PORT_80_MULTI_BYTE
	bool "Host can write 1/2/4 bytes of Port80 data in a eSPI transaction"
	depends on (SOC_SERIES_NPCX9 || SOC_SERIES_NPCX4) && ESPI_PERIPHERAL_DEBUG_PORT_80
	select RING_BUFFER
	help
	  EC can accept 1/2/4 bytes of Port 80 data written from the Host in an
	  eSPI transaction.

config ESPI_NPCX_PERIPHERAL_DEBUG_PORT_80_RING_BUF_SIZE
	int "Debug Port80 ring buffer size"
	depends on ESPI_NPCX_PERIPHERAL_DEBUG_PORT_80_MULTI_BYTE
	default 256
	help
	  The size of the ring buffer in byte used by the Port80 ISR to store
	  Postcodes from Host.

config ESPI_TAF_NPCX
	bool "Nuvoton NPCX embedded controller (EC) ESPI TAF driver"
	depends on SOC_SERIES_NPCX4
	depends on FLASH
	help
	  This option enables the Intel Enhanced Serial Peripheral Interface
	  Target Attached Flash (eSPI TAF) for NPCX4 family of processors.

choice ESPI_TAF_ACCESS_MODE_CHOICE
	prompt "eSPI TAF Read Access Mode"
	default ESPI_TAF_AUTO_MODE

config ESPI_TAF_AUTO_MODE
	bool "eSPI TAF Automatic Mode"
	help
	  This is the setting to use auto mode for eSPI TAF read.

config ESPI_TAF_MANUAL_MODE
	bool "eSPI TAF Manual Mode"
	help
	  This is the setting to use manual mode for eSPI TAF read.

endchoice

config ESPI_TAF_PR_NUM
	int "Sets of protection region settings"
	default 16
	help
	  This size is display how many group of slave attached flash protection
	  region.

config ESPI_TAF_NPCX_RPMC_SUPPORT
	bool "eSPI TAF RPMC support"
	depends on ESPI_TAF_NPCX
	select FLASH_EX_OP_ENABLED
	help
	  This option enable the handler for eSPI TAF RPMC request.

# The default value 'y' for the existing options if ESPI_NPCX is selected.
if ESPI_NPCX

config ESPI_OOB_CHANNEL
	default  y

config ESPI_PERIPHERAL_8042_KBC
	default y

config ESPI_PERIPHERAL_HOST_IO
	default y

config ESPI_PERIPHERAL_DEBUG_PORT_80
	default y

config ESPI_PERIPHERAL_EC_HOST_CMD
	default y

config ESPI_PERIPHERAL_ACPI_SHM_REGION
	default y

config ESPI_PERIPHERAL_CUSTOM_OPCODE
	default y

config ESPI_NPCX_SUPP_VW_GPIO
	bool "Indicates that the eSPI hardware supports virtual wire GPIOs"
	default y if SOC_SERIES_NPCX9 || SOC_SERIES_NPCX4
	help
	  Selected if NPCX series supports virtual wire GPIOs in eSPI module.

config ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND
	bool
	default y if SOC_SERIES_NPCX4 && ESPI_FLASH_CHANNEL
	help
	  Workaround the issue "Global Reset" in the npcx4 SoC errata.

config ESPI_NPCX_RESET_SLP_SX_VW_ON_ESPI_RST
	bool "Reset SLP_Sx virtual wires when eSPI_RST is asserted"
	help
	    The SLP_S3/SLP_S4/SLP_S5/ virtual wires are automatically reset when
	    eSPI_Reset is asserted on the global reset.
	    Don't enable this config if the platform implements the Deep-Sx
	    entry as EC needs to maintain these pins' states per request.

endif #ESPI_NPCX