| /* |
| * Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk> |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <mem.h> |
| |
| / { |
| chosen { |
| zephyr,console = &uartlite0; |
| zephyr,shell-uart = &uartlite0; |
| zephyr,flash = &itcm; |
| /* Use DTCM as SRAM by default */ |
| zephyr,sram = &dtcm; |
| }; |
| |
| aliases { |
| led0 = &led_ld4; |
| led1 = &led_ld5; |
| led2 = &led_ld6; |
| led3 = &led_ld7; |
| sw0 = &sw0; |
| sw1 = &sw1; |
| sw2 = &sw2; |
| sw3 = &sw3; |
| spi-flash0 = &flash0; |
| }; |
| |
| leds { |
| compatible = "gpio-leds"; |
| led_ld0_red: led_ld0_red { |
| gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; |
| label = "LED LD0 RED"; |
| }; |
| led_ld0_green: led_ld0_green { |
| gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; |
| label = "LED LD0 GREEN"; |
| }; |
| led_ld0_blue: led_ld0_blue { |
| gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; |
| label = "LED LD0 BLUE"; |
| }; |
| |
| led_ld1_red: led_ld1_red { |
| gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; |
| label = "LED LD1 RED"; |
| }; |
| led_ld1_green: led_ld1_green { |
| gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; |
| label = "LED LD1 GREEN"; |
| }; |
| led_ld1_blue: led_ld1_blue { |
| gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; |
| label = "LED LD1 BLUE"; |
| }; |
| |
| led_ld2_red: led_ld2_red { |
| gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; |
| label = "LED LD2 RED"; |
| }; |
| led_ld2_green: led_ld2_green { |
| gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; |
| label = "LED LD2 GREEN"; |
| }; |
| led_ld2_blue: led_ld2_blue { |
| gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; |
| label = "LED LD2 BLUE"; |
| }; |
| |
| led_ld3_red: led_ld3_red { |
| gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; |
| label = "LED LD3 RED"; |
| }; |
| led_ld3_green: led_ld3_green { |
| gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; |
| label = "LED LD3 GREEN"; |
| }; |
| led_ld3_blue: led_ld3_blue { |
| gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; |
| label = "LED LD3 BLUE"; |
| }; |
| |
| led_ld4: led_ld4 { |
| gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; |
| label = "LED LD4"; |
| }; |
| led_ld5: led_ld5 { |
| gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; |
| label = "LED LD5"; |
| }; |
| led_ld6: led_ld6 { |
| gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; |
| label = "LED LD6"; |
| }; |
| led_ld7: led_ld7 { |
| gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; |
| label = "LED LD7"; |
| }; |
| }; |
| |
| gpio_keys { |
| compatible = "gpio-keys"; |
| sw0: sw0 { |
| gpios = <&gpio0_2 0 GPIO_ACTIVE_HIGH>; |
| label = "SW0"; |
| }; |
| sw1: sw1 { |
| gpios = <&gpio0_2 1 GPIO_ACTIVE_HIGH>; |
| label = "SW1"; |
| }; |
| sw2: sw2 { |
| gpios = <&gpio0_2 2 GPIO_ACTIVE_HIGH>; |
| label = "SW2"; |
| }; |
| sw3: sw3 { |
| gpios = <&gpio0_2 3 GPIO_ACTIVE_HIGH>; |
| label = "SW3"; |
| }; |
| btn0: btn0 { |
| gpios = <&gpio1_2 0 GPIO_ACTIVE_HIGH>; |
| label = "BTN0"; |
| }; |
| btn1: btn1 { |
| gpios = <&gpio1_2 1 GPIO_ACTIVE_HIGH>; |
| label = "BTN1"; |
| }; |
| btn2: btn2 { |
| gpios = <&gpio1_2 2 GPIO_ACTIVE_HIGH>; |
| label = "BTN2"; |
| }; |
| btn3: btn3 { |
| gpios = <&gpio1_2 3 GPIO_ACTIVE_HIGH>; |
| label = "BTN3"; |
| }; |
| }; |
| |
| daplink_qspi_mux: daplink_qspi_mux { |
| compatible = "arm,daplink-qspi-mux"; |
| status = "disabled"; |
| interrupt-parent = <&nvic>; |
| interrupts = <7 0>; |
| mux-gpios = <&daplink_gpio0 0 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| soc { |
| daplink_gpio0: gpio@40010000 { |
| compatible = "xlnx,xps-gpio-1.00.a"; |
| status = "disabled"; |
| reg = <0x40010000 0x10000>; |
| label = "DAPLINK_GPIO_0"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| xlnx,all-inputs = <0x0>; |
| xlnx,all-outputs = <0x0>; |
| xlnx,dout-default = <0x0>; |
| xlnx,gpio-width = <0x20>; |
| xlnx,is-dual = <0x0>; |
| xlnx,tri-default = <0xffffffff>; |
| }; |
| |
| daplink_quad_spi0: spi@40020000 { |
| compatible = "xlnx,xps-spi-2.00.a"; |
| status = "disabled"; |
| reg = <0x40020000 0x10000>; |
| interrupts = <4 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| label = "DAPLINK_QUAD_SPI_0"; |
| |
| xlnx,num-ss-bits = <0x1>; |
| xlnx,num-transfer-bits = <0x8>; |
| }; |
| |
| daplink_single_spi0: spi@40030000 { |
| compatible = "xlnx,xps-spi-2.00.a"; |
| status = "disabled"; |
| reg = <0x40030000 0x10000>; |
| interrupts = <5 0>; |
| label = "DAPLINK_SINGLE_SPI_0"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| xlnx,num-ss-bits = <0x1>; |
| xlnx,num-transfer-bits = <0x8>; |
| }; |
| |
| uartlite0: uartlite@40100000 { |
| compatible = "xlnx,xps-uartlite-1.00.a"; |
| interrupts = <0 0>; |
| reg = <0x40100000 0x10000>; |
| label = "UART_0"; |
| }; |
| |
| gpio0: gpio@40110000 { |
| compatible = "xlnx,xps-gpio-1.00.a"; |
| interrupts = <1 0>; |
| reg = <0x40110000 0x10000>; |
| label = "GPIO_0"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| xlnx,all-inputs = <0x0>; |
| xlnx,all-inputs-2 = <0x1>; |
| xlnx,all-outputs = <0x0>; |
| xlnx,all-outputs-2 = <0x0>; |
| xlnx,dout-default = <0x0>; |
| xlnx,dout-default-2 = <0x0>; |
| xlnx,gpio-width = <0x4>; |
| xlnx,gpio2-width = <0x4>; |
| xlnx,is-dual = <0x1>; |
| xlnx,tri-default = <0xffffffff>; |
| xlnx,tri-default-2 = <0xffffffff>; |
| |
| gpio0_2: gpio2 { |
| compatible = "xlnx,xps-gpio-1.00.a-gpio2"; |
| label = "GPIO_0_2"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| }; |
| |
| gpio1: gpio@40120000 { |
| compatible = "xlnx,xps-gpio-1.00.a"; |
| interrupts = <2 0>; |
| reg = <0x40120000 0x10000>; |
| label = "GPIO_1"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| xlnx,all-inputs = <0x0>; |
| xlnx,all-inputs-2 = <0x1>; |
| xlnx,all-outputs = <0x0>; |
| xlnx,all-outputs-2 = <0x0>; |
| xlnx,dout-default = <0x0>; |
| xlnx,dout-default-2 = <0x0>; |
| xlnx,gpio-width = <0xc>; |
| xlnx,gpio2-width = <0x4>; |
| xlnx,is-dual = <0x1>; |
| xlnx,tri-default = <0xffffffff>; |
| xlnx,tri-default-2 = <0xffffffff>; |
| |
| gpio1_2: gpio2 { |
| compatible = "xlnx,xps-gpio-1.00.a-gpio2"; |
| label = "GPIO_1_2"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| }; |
| |
| quad_spi0: spi@40130000 { |
| compatible = "xlnx,xps-spi-2.00.a"; |
| reg = <0x40130000 0x10000>; |
| interrupts = <3 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| label = "QUAD_SPI_0"; |
| |
| xlnx,num-ss-bits = <0x1>; |
| xlnx,num-transfer-bits = <0x8>; |
| |
| flash0: flash@0 { |
| compatible = "micron,n25q128a","jedec,spi-nor"; |
| reg = <0>; |
| spi-max-frequency = <108000000>; |
| size = <DT_SIZE_M(128)>; |
| jedec-id = [20 ba 18]; |
| label = "FLASH_0"; |
| |
| partitions { |
| compatible = "fixed-partitions"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| fpga_bitstream_partition: partition@0 { |
| label = "fpga_bitstream"; |
| /* From Xilinx 7 Series FPGA User Guide (UG470) |
| * Table 1-1: Bitstream Length |
| * Bits Bytes (sector multiple) |
| * A35T: 17,536,096 0x218000 |
| * A100T: 30,606,304 0x3a8000 |
| */ |
| reg = <0x00000000 0x218000>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| }; |
