| # Copyright (c) 2020 STMicroelectronics |
| # |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| if BOARD_NUCLEO_F411RE |
| |
| if I2S |
| |
| # The I2S should be configured in such a way it generates a 2MHz |
| # clock to the MP34DT05 microphone. |
| # |
| # The input clock to I2S block is I2SClk. This clock is generated |
| # by the PLLI2S from either HSI or HSE osci using this formula: |
| # |
| # Fin = HSE or HSI osci |
| # Fvco = Fin x (PLLN/PLLM) |
| # I2SClk = Fvco / PLLR |
| # |
| # For example, if Fin is HSE at 8MHz and PLLM=8, PLLN=192, PLLR=3, |
| # the resulting I2SCLk is 64MHz. On the contrary if HSI at 16MHz is |
| # used the resulting I2SClk frequency would be 128MHz. |
| # The shield user is invited to verify which osci is configured on |
| # Nucleo F441RE board defconfig file and calculate the final frequency. |
| # |
| # The I2S block then uses I2SDIV and I2SODD register fields to further |
| # divide I2SClk. These parameters are automatically calculated by |
| # I2S driver, in order to obtain the requested output @2MHz, so |
| # having a I2SClk in input at 64MHz or 128MHz does not make a any |
| # difference. |
| |
| config I2S_STM32_USE_PLLI2S_ENABLE |
| default y |
| |
| config I2S_STM32_PLLI2S_PLLM |
| default 8 |
| |
| config I2S_STM32_PLLI2S_PLLN |
| default 192 |
| |
| config I2S_STM32_PLLI2S_PLLR |
| default 3 |
| |
| endif # I2S |
| |
| endif # BOARD_NUCLEO_F411RE |
