dts/arm/quicklogic/quicklogic_eos_s3.dtsi

/*
 * Copyright (c) 2020 Antmicro <www.antmicro.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <arm/armv7-m.dtsi>
#include <zephyr/dt-bindings/gpio/gpio.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m4f";
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <1>;

			mpu: mpu@e000ed90 {
				compatible = "arm,armv7m-mpu";
				reg = <0xe000ed90 0x40>;
				arm,num-mpu-regions = <8>;
			};
		};
	};

	sram0: memory@20000000 {
		compatible = "mmio-sram";
		reg = <0x20000000 DT_SIZE_K(512)>;
	};

	uartclk: uart-clock {
		compatible = "fixed-clock";
		clock-frequency = <5120000>;
		#clock-cells = <0>;
	};

	soc {
		uart0: uart@40010000 {
			compatible = "arm,pl011";
			reg = <0x40010000 DT_SIZE_K(4)>;
			clocks = <&uartclk>;
			interrupts = <7 3>;
			interrupt-names = "rx";
		};

		gpio: gpio {
			compatible = "quicklogic,eos-s3-gpio";
			status = "disabled";
			interrupts = <5 2>;
			#gpio-cells = <2>;
			ngpios = <8>;
			pin-secondary-config = <0x00>;
			gpio-controller;
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};