blob: e9568ef168553c412d4f259e99ce4dac03767d37 [file] [log] [blame]
/*
* Copyright (c) 2018 Philémon Jaermann
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f401.dtsi>
#include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
/ {
soc {
i2s1: i2s@40013000 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
interrupts = <35 5>;
dmas = <&dma2 3 3 0x400 0x3
&dma2 2 3 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
interrupts = <39 0>;
status = "disabled";
};
uart4: serial@40004c00 {
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <52 0>;
status = "disabled";
};
uart5: serial@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
interrupts = <53 0>;
status = "disabled";
};
can1: can@40006400 {
compatible = "st,stm32-can";
reg = <0x40006400 0x400>;
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
status = "disabled";
sjw = <1>;
sample-point = <875>;
};
can2: can@40006800 {
compatible = "st,stm32-can";
reg = <0x40006800 0x400>;
interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
/* also enabling clock for can1 (master instance) */
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
master-can-reg = <0x40006400>;
status = "disabled";
sjw = <1>;
sample-point = <875>;
};
usbotg_fs: usb@50000000 {
num-bidir-endpoints = <6>;
};
usbotg_hs: usb@40040000 {
compatible = "st,stm32-otghs";
reg = <0x40040000 0x40000>;
interrupts = <77 0>, <74 0>, <75 0>;
interrupt-names = "otghs", "ep1_out", "ep1_in";
num-bidir-endpoints = <9>;
ram-size = <4096>;
maximum-speed = "full-speed";
phys = <&otghs_fs_phy>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>;
status = "disabled";
};
backup_sram: memory@40024000 {
compatible = "zephyr,memory-region", "st,stm32-backup-sram";
reg = <0x40024000 DT_SIZE_K(4)>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
zephyr,memory-region = "BACKUP_SRAM";
status = "disabled";
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
#io-channel-cells = <1>;
};
fmc: memory-controller@a0000000 {
compatible = "st,stm32-fmc";
reg = <0xa0000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
status = "disabled";
sdram: sdram {
compatible = "st,stm32-fmc-sdram";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};
otghs_fs_phy: otghs_fs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};