blob: 56bddda1dd21029e7389ba317e6eb1bb396e89cb [file] [log] [blame]
description: nRFx S/W PWM
compatible: "nordic,nrf-sw-pwm"
include: [pwm-controller.yaml, base.yaml]
properties:
generator:
type: phandle
required: true
description: |
Reference to TIMER or RTC instance for generating PWM output signals
clock-prescaler:
type: int
required: true
description: |
Clock prescaler for RTC or TIMER used for generating PWM output signals.
RTC: needs to be set to 0, which gives 32768 Hz base clock for PWM
generation.
TIMER: 16 MHz / 2^prescaler base clock is used for PWM generation.
channel-gpios:
type: phandle-array
required: true
description: |
An array of GPIOs assigned as outputs for the PWM channels. The number
of items in this array determines the number of channels that this PWM
will provide. This value is limited by the number of compare registers
in the used RTC/TIMER instance minus 1.
Example:
sw_pwm: sw-pwm {
compatible = "nordic,nrf-sw-pwm";
...
channel-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>,
<&gpio1 12 GPIO_ACTIVE_HIGH>;
...
};
The above will assign P0.20 as the output for channel 0 and P1.12 as
the output for channel 1. Both outputs will be initially configured as
active high.
Please note that in the flags cell (the last component of each item
of the array) only the GPIO flags that specify the active level are
taken into account (any others are ignored), and they are used only
when the initial (inactive) state of the outputs is set.
After any PWM signal generation is requested for a given channel,
the polarity of its output is determined by the flag specified
in the request, i.e. PWM_POLARITY_INVERTED or PWM_POLARITY_NORMAL.
"#pwm-cells":
const: 3
pwm-cells:
- channel
- period
- flags