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github
/
zephyrproject-rtos
/
zephyr
/
aaaed300713d241bb222feb769b43eb32c446b33
/
.
/
samples
/
modules
/
sof
/
boards
/
intel_adsp_cavs25.conf
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CONFIG_TIGERLAKE
=
y
CONFIG_INTEL_DMIC
=
y
CONFIG_INTEL_SSP
=
y
CONFIG_INTEL_ALH
=
y
CONFIG_LP_MEMORY_BANKS
=
1
CONFIG_HP_MEMORY_BANKS
=
30
CONFIG_RIMAGE_SIGNING_SCHEMA
=
"tgl"
