boards/xtensa/esp32/esp32.dts

/*
 * Copyright (c) 2019 Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */
/dts-v1/;

#include <espressif/esp32.dtsi>

/ {
	model = "esp32";
	compatible = "espressif,esp32";

	aliases {
		uart-0 = &uart0;
		i2c-0 = &i2c0;
	};

	chosen {
		zephyr,sram = &sram0;
		zephyr,console = &uart0;
		zephyr,shell-uart = &uart0;
		zephyr,flash = &flash0;
	};
};

&cpu0 {
	clock-frequency = <ESP32_CLK_CPU_240M>;
};

&cpu1 {
	clock-frequency = <ESP32_CLK_CPU_240M>;
};

&uart0 {
	status = "okay";
	current-speed = <115200>;
	tx-pin = <1>;
	rx-pin = <3>;
	rts-pin = <22>;
	cts-pin = <19>;
};

&uart1 {
	current-speed = <115200>;
	tx-pin = <10>;
	rx-pin = <9>;
	rts-pin = <11>;
	cts-pin = <6>;
	hw-flow-control;
};

&uart2 {
	current-speed = <115200>;
	tx-pin = <17>;
	rx-pin = <16>;
	rts-pin = <7>;
	cts-pin = <8>;
	hw-flow-control;
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&i2c0 {
	status = "okay";
	clock-frequency = <I2C_BITRATE_STANDARD>;
	sda-pin = <21>;
	scl-pin = <22>;
};

&i2c1 {
	clock-frequency = <I2C_BITRATE_STANDARD>;
	sda-pin = <18>;
	scl-pin = <5>;
};

&spi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	miso-pin = <12>;
	mosi-pin = <13>;
	sclk-pin = <14>;
	csel-pin = <15>;
};

&spi3 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	miso-pin = <19>;
	mosi-pin = <23>;
	sclk-pin = <18>;
	csel-pin = <5>;
};

&timer0 {
	status = "okay";
};

&timer1 {
	status = "okay";
};

&timer2 {
	status = "okay";
};

&timer3 {
	status = "okay";
};

&trng0 {
	status = "okay";
};

&flash0 {
	status = "okay";
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		storage_partition: partition@9000 {
			label = "storage";
			reg = <0x00009000 0x00006000>;
		};
	};
};