| # Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or |
| # an affiliate of Cypress Semiconductor Corporation |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| # Infineon CAT1A devices |
| |
| # Family definitions |
| config SOC_FAMILY_PSOC6 |
| select ARM |
| select CPU_CORTEX_M4 |
| select CPU_HAS_ARM_MPU |
| select DYNAMIC_INTERRUPTS |
| select CPU_HAS_FPU |
| select SOC_FAMILY_INFINEON_CAT1 |
| |
| config SOC_FAMILY_PSOC6_LEGACY |
| select ARM |
| select HAS_CYPRESS_DRIVERS |
| select CPU_CORTEX_M_HAS_SYSTICK |
| select CPU_HAS_ARM_MPU |
| |
| config SOC_FAMILY_PSOC6_LEGACY_M4 |
| select CPU_CORTEX_M4 |
| select CPU_CORTEX_M_HAS_DWT |
| select CPU_HAS_FPU |
| |
| config SOC_FAMILY_PSOC6_LEGACY_M0 |
| select CPU_CORTEX_M0PLUS |
| select CPU_CORTEX_M_HAS_VTOR |
| |
| config SOC_PSOC6_M0_ENABLES_M4 |
| bool "Dual-core support [activate Cortex-M4]" |
| depends on SOC_FAMILY_PSOC6_LEGACY_M0 |
| help |
| Cortex-M0 CPU should boot Cortex-M4 |
| |
| if SOC_FAMILY_PSOC6 |
| ## PSOC™ 6 Cortex M0+ prebuilt images |
| choice |
| prompt "PSOC™ 6 Cortex M0+ prebuilt images" |
| help |
| Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSOC™ 6 |
| dual-core MCU. The image is responsible for booting the Cortex-M4 on the device. |
| |
| config SOC_PSOC6_CM0P_IMAGE_SLEEP |
| bool "DeepSleep" |
| help |
| DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSOC™ 6 BLE |
| dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4 |
| application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4 |
| linker script. |
| endchoice |
| |
| config SOC_PSOC6_CM0P_IMAGE_ROM_SIZE |
| hex |
| default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP |
| |
| config SOC_PSOC6_CM0P_IMAGE_RAM_SIZE |
| hex |
| default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP |
| |
| endif # SOC_FAMILY_PSOC6 |
