tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_sysclk.overlay

/*
 * Copyright (c) 2021 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Warning: This overlay performs configuration from clean sheet.
 * It is assumed that it is applied after core_init.overlay file.
 */

&spi1 {
	/delete-property/ clocks;
	clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
			<&rcc STM32_SRC_SYSCLK SPI1_SEL(1)>;
	status = "okay";
};