| /* |
| * Copyright 2023 NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h> |
| |
| &iomuxc { |
| iomuxc_uart2_rx_uart2_rx: IOMUXC_UART2_RX_UART2_RX { |
| pinmux = <SC_P_UART2_RX IMX8QXP_DMA_LPUART2_RX_UART2_RX>; |
| }; |
| |
| iomuxc_uart2_tx_uart2_tx: IOMUXC_UART2_TX_UART2_TX { |
| pinmux = <SC_P_UART2_TX IMX8QXP_DMA_LPUART2_TX_UART2_TX>; |
| }; |
| |
| iomuxc_adma_sai1_txfs_sai1_rxfs: IOMUXC_ADMA_SAI1_TXFS_SAI1_RXFS { |
| pinmux = <SC_P_SAI1_RXFS IMX8QXP_ADMA_SAI1_TXFS_SAI1_RXFS>; |
| }; |
| |
| iomuxc_adma_sai1_rxd_sai1_rxd: IOMUXC_ADMA_SAI1_RXD_SAI1_RXD { |
| pinmux = <SC_P_SAI1_RXD IMX8QXP_ADMA_SAI1_RXD_SAI1_RXD>; |
| }; |
| |
| iomuxc_adma_sai1_txc_sai1_rxc: IOMUXC_ADMA_SAI1_TXC_SAI1_RXC { |
| pinmux = <SC_P_SAI1_RXC IMX8QXP_ADMA_SAI1_TXC_SAI1_RXC>; |
| }; |
| |
| iomuxc_adma_sai1_txd_spi0_cs1: IOMUXC_ADMA_SAI1_TXD_SPI0_CS1 { |
| pinmux = <SC_P_SPI0_CS1 IMX8QXP_ADMA_SAI1_TXD_SPI0_CS1>; |
| }; |
| }; |
| |
| &pinctrl { |
| lpuart2_default: lpuart2_default { |
| group0 { |
| pinmux = <&iomuxc_uart2_rx_uart2_rx>, |
| <&iomuxc_uart2_tx_uart2_tx>; |
| }; |
| }; |
| |
| sai1_default: sai1_default { |
| group0 { |
| pinmux = <&iomuxc_adma_sai1_txfs_sai1_rxfs>, |
| <&iomuxc_adma_sai1_rxd_sai1_rxd>, |
| <&iomuxc_adma_sai1_txc_sai1_rxc>, |
| <&iomuxc_adma_sai1_txd_spi0_cs1>; |
| }; |
| }; |
| }; |