dts/arm/st/f0/stm32f030Xc.dtsi

/*
 * Copyright (c) 2018 Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <st/f0/stm32f030.dtsi>

/ {
	sram0: memory@20000000 {
		reg = <0x20000000 DT_SIZE_K(32)>;
	};

	soc {
		flash-controller@40022000 {
			flash0: flash@8000000 {
				reg = <0x08000000 DT_SIZE_K(256)>;
			};
		};

		spi2: spi@40003800 {
			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
			interrupts = <26 3>;
			status = "disabled";
		};

		/*
		 * USARTs 3-6 share the same IRQ on stm32f030Xc devices. This
		 * configuration is not currently supported, so at most one of
		 * these may be enabled at a time. Enabling more than one will
		 * result in a build failure.
		 */
		usart3: serial@40004800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
			interrupts = <29 0>;
			status = "disabled";
		};

		usart4: serial@40004c00 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
			interrupts = <29 0>;
			status = "disabled";
		};

		usart5: serial@40005000 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40005000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
			interrupts = <29 0>;
			status = "disabled";
		};

		usart6: serial@40011400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
			interrupts = <29 0>;
			status = "disabled";
		};
	};
};