| /* |
| * Copyright (c) 2018 Yurii Hamann |
| * Copyright (c) 2019 Centaur Analytics, Inc |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv7-m.dtsi> |
| #include <dt-bindings/clock/stm32_clock.h> |
| #include <dt-bindings/i2c/i2c.h> |
| #include <dt-bindings/gpio/gpio.h> |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m7"; |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| mpu: mpu@e000ed90 { |
| compatible = "arm,armv7m-mpu"; |
| reg = <0xe000ed90 0x40>; |
| arm,num-mpu-regions = <8>; |
| }; |
| }; |
| }; |
| |
| soc { |
| flash-controller@40023c00 { |
| compatible = "st,stm32f7-flash-controller"; |
| label = "FLASH_CTRL"; |
| reg = <0x40023c00 0x400>; |
| interrupts = <4 0>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "soc-nv-flash"; |
| label = "FLASH_STM32"; |
| |
| write-block-size = <1>; |
| }; |
| }; |
| rcc: rcc@40023800 { |
| compatible = "st,stm32-rcc"; |
| #clock-cells = <2>; |
| reg = <0x40023800 0x400>; |
| label = "STM32_CLK_RCC"; |
| }; |
| |
| pinctrl: pin-controller@40020000 { |
| compatible = "st,stm32-pinmux"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x40020000 0x2400>; |
| |
| gpioa: gpio@40020000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40020000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>; |
| label = "GPIOA"; |
| }; |
| |
| gpiob: gpio@40020400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40020400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>; |
| label = "GPIOB"; |
| }; |
| |
| gpioc: gpio@40020800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40020800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>; |
| label = "GPIOC"; |
| }; |
| |
| gpiod: gpio@40020C00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40020C00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>; |
| label = "GPIOD"; |
| }; |
| |
| gpioe: gpio@40021000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40021000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>; |
| label = "GPIOE"; |
| }; |
| |
| gpiof: gpio@40021400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40021400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>; |
| label = "GPIOF"; |
| }; |
| |
| gpiog: gpio@40021800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40021800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>; |
| label = "GPIOG"; |
| }; |
| |
| gpioh: gpio@40021C00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40021C00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>; |
| label = "GPIOH"; |
| }; |
| |
| gpioi: gpio@40022000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x40022000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>; |
| label = "GPIOI"; |
| }; |
| }; |
| |
| iwdg: watchdog@40003000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x40003000 0x400>; |
| label = "IWDG"; |
| status = "disabled"; |
| }; |
| |
| wwdg: watchdog@40002c00 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x40002C00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; |
| label = "WWDG"; |
| interrupts = <0 7>; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@40011000 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40011000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>; |
| interrupts = <37 0>; |
| status = "disabled"; |
| label = "UART_1"; |
| }; |
| |
| usart2: serial@40004400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; |
| interrupts = <38 0>; |
| status = "disabled"; |
| label = "UART_2"; |
| }; |
| |
| usart3: serial@40004800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; |
| interrupts = <39 0>; |
| status = "disabled"; |
| label = "UART_3"; |
| }; |
| |
| uart4: serial@40004c00 { |
| compatible ="st,stm32-uart"; |
| reg = <0x40004c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; |
| interrupts = <52 0>; |
| status = "disabled"; |
| label = "UART_4"; |
| }; |
| |
| uart5: serial@40005000 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40005000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>; |
| interrupts = <53 0>; |
| status = "disabled"; |
| label = "UART_5"; |
| }; |
| |
| usart6: serial@40011400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40011400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>; |
| interrupts = <71 0>; |
| status = "disabled"; |
| label = "UART_6"; |
| }; |
| |
| uart7: serial@40007800 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40007800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>; |
| interrupts = <82 0>; |
| status = "disabled"; |
| label = "UART_7"; |
| }; |
| |
| uart8: serial@40007c00 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40007c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>; |
| interrupts = <83 0>; |
| status = "disabled"; |
| label = "UART_8"; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>; |
| interrupts = <31 0>, <32 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| label = "I2C_1"; |
| }; |
| |
| i2c2: i2c@40005800 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; |
| interrupts = <33 0>, <34 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| label = "I2C_2"; |
| }; |
| |
| i2c3: i2c@40005c00 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>; |
| interrupts = <72 0>, <73 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| label = "I2C_3"; |
| }; |
| |
| spi1: spi@40013000 { |
| compatible = "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>; |
| interrupts = <35 5>; |
| status = "disabled"; |
| label = "SPI_1"; |
| }; |
| |
| spi2: spi@40003800 { |
| compatible = "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; |
| interrupts = <36 5>; |
| status = "disabled"; |
| label = "SPI_2"; |
| }; |
| |
| spi3: spi@40003c00 { |
| compatible = "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>; |
| interrupts = <51 5>; |
| status = "disabled"; |
| label = "SPI_3"; |
| }; |
| |
| spi4: spi@40013400 { |
| compatible = "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>; |
| interrupts = <84 5>; |
| status = "disabled"; |
| label = "SPI_4"; |
| }; |
| |
| spi5: spi@40015000 { |
| compatible = "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40015000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>; |
| interrupts = <85 5>; |
| status = "disabled"; |
| label = "SPI_5"; |
| }; |
| |
| spi6: spi@40015400 { |
| compatible = "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40015400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>; |
| interrupts = <86 5>; |
| status = "disabled"; |
| label = "SPI_6"; |
| }; |
| |
| can1: can@40006400 { |
| compatible = "st,stm32-can"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40006400 0x400>; |
| interrupts = <19 0>, <20 0>, <21 0>, <22 0>; |
| interrupt-names = "TX", "RX0", "RX1", "SCE"; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; |
| status = "disabled"; |
| label = "CAN_1"; |
| }; |
| |
| timers1: timers@40010000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40010000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>; |
| status = "disabled"; |
| label = "TIMERS_1"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_1"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers2: timers@40000000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>; |
| status = "disabled"; |
| label = "TIMERS_2"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <0>; |
| label = "PWM_2"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers3: timers@40000400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; |
| status = "disabled"; |
| label = "TIMERS_3"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_3"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers4: timers@40000800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>; |
| status = "disabled"; |
| label = "TIMERS_4"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_4"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers5: timers@40000c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>; |
| status = "disabled"; |
| label = "TIMERS_5"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <0>; |
| label = "PWM_5"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers6: timers@40001000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>; |
| status = "disabled"; |
| label = "TIMERS_6"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_6"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers7: timers@40001400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>; |
| status = "disabled"; |
| label = "TIMERS_7"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_7"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers8: timers@40010400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40010400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>; |
| status = "disabled"; |
| label = "TIMERS_8"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_8"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers9: timers@40014000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>; |
| status = "disabled"; |
| label = "TIMERS_9"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_9"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers10: timers@40014400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>; |
| status = "disabled"; |
| label = "TIMERS_10"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_10"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers11: timers@40014800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>; |
| status = "disabled"; |
| label = "TIMERS_11"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_11"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers12: timers@40001800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>; |
| status = "disabled"; |
| label = "TIMERS_12"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_12"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers13: timers@40001c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>; |
| status = "disabled"; |
| label = "TIMERS_13"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_13"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers14: timers@40002000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40002000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>; |
| status = "disabled"; |
| label = "TIMERS_14"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_14"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| usbotg_fs: usb@50000000 { |
| compatible = "st,stm32-otgfs"; |
| reg = <0x50000000 0x40000>; |
| interrupts = <67 0>; |
| interrupt-names = "otgfs"; |
| num-bidir-endpoints = <6>; |
| ram-size = <1280>; |
| maximum-speed = "full-speed"; |
| phys = <&otgfs_phy>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>; |
| status = "disabled"; |
| label = "OTGFS"; |
| }; |
| |
| usbotg_hs: usb@40040000 { |
| compatible = "st,stm32-otghs", "st,stm32-otgfs"; |
| reg = <0x40040000 0x40000>; |
| interrupts = <77 0>, <74 0>, <75 0>; |
| interrupt-names = "otghs", "ep1_out", "ep1_in"; |
| num-bidir-endpoints = <9>; |
| ram-size = <4096>; |
| maximum-speed = "full-speed"; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>; |
| phys = <&otghs_fs_phy>; |
| status = "disabled"; |
| label= "OTGHS"; |
| }; |
| |
| rtc: rtc@40002800 { |
| compatible = "st,stm32-rtc"; |
| reg = <0x40002800 0x300>; |
| interrupts = <41 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>; |
| prescaler = <32768>; |
| status = "disabled"; |
| label = "RTC_0"; |
| }; |
| |
| adc1: adc@40012000 { |
| compatible = "st,stm32-adc"; |
| reg = <0x40012000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>; |
| interrupts = <18 0>; |
| status = "disabled"; |
| label = "ADC_1"; |
| #io-channel-cells = <1>; |
| }; |
| |
| dma1: dma@40026000 { |
| compatible = "st,stm32-dma"; |
| #dma-cells = <4>; |
| reg = <0x40026000 0x400>; |
| interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>; |
| status = "disabled"; |
| label = "DMA_1"; |
| }; |
| |
| dma2: dma@40026400 { |
| compatible = "st,stm32-dma"; |
| #dma-cells = <4>; |
| reg = <0x40026400 0x400>; |
| interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>; |
| st,mem2mem; |
| status = "disabled"; |
| label = "DMA_2"; |
| }; |
| }; |
| |
| otghs_fs_phy: otghs_fs_phy { |
| compatible = "usb-nop-xceiv"; |
| #phy-cells = <0>; |
| label = "OTGHS_FS_PHY"; |
| }; |
| |
| otgfs_phy: otgfs_phy { |
| compatible = "usb-nop-xceiv"; |
| #phy-cells = <0>; |
| label = "OTGFS_PHY"; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
