boards: s32z270dc2_r52: document supported features
Document supported features and do minor refactoring.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
diff --git a/boards/arm/s32z270dc2_r52/doc/index.rst b/boards/arm/s32z270dc2_r52/doc/index.rst
index 2267b49..d6d3427 100644
--- a/boards/arm/s32z270dc2_r52/doc/index.rst
+++ b/boards/arm/s32z270dc2_r52/doc/index.rst
@@ -29,9 +29,17 @@
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
-| GIC | on-chip | interrupt_controller |
+| Arm GIC | on-chip | interrupt_controller |
+-----------+------------+-------------------------------------+
-| ARM Timer | on-chip | timer |
+| Arm Timer | on-chip | timer |
++-----------+------------+-------------------------------------+
+| LINFlexD | on-chip | serial |
++-----------+------------+-------------------------------------+
+| MRU | on-chip | mbox |
++-----------+------------+-------------------------------------+
+| NETC | on-chip | ethernet |
+| | | |
+| | | mdio |
+-----------+------------+-------------------------------------+
| SIUL2 | on-chip | pinctrl |
| | | |
@@ -39,8 +47,6 @@
| | | |
| | | external interrupt controller |
+-----------+------------+-------------------------------------+
-| LINFlexD | on-chip | serial |
-+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| SWT | on-chip | watchdog |
@@ -110,8 +116,17 @@
Watchdog
========
-Currently Watchdog only supports interrupt triggering, but does not support
-reset function because currently the board does not support running on flash.
+The watchdog driver only supports triggering an interrupt upon timer expiration.
+Zephyr is currently running from SRAM on this board, thus system reset is not
+supported.
+
+Ethernet
+========
+
+NETC driver supports to manage the Physical Station Interface (PSI0) and/or a
+single Virtual SI (VSI). The rest of the VSI's shall be assigned to different
+cores of the system. Refer to :ref:`nxp_s32_netc-samples` to learn how to
+configure the Ethernet network controller.
Programming and Debugging
*************************
diff --git a/samples/boards/nxp_s32/netc/README.rst b/samples/boards/nxp_s32/netc/README.rst
index 51b372b..f779dcf 100644
--- a/samples/boards/nxp_s32/netc/README.rst
+++ b/samples/boards/nxp_s32/netc/README.rst
@@ -1,4 +1,4 @@
-.. nxp_s32_netc-samples:
+.. _nxp_s32_netc-samples:
NXP S32 NETC Sample Application
###############################
