| /* |
| * Copyright (c) 2017-2022, NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ |
| #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ |
| |
| /* |
| * Define 16 bits clock ID: 0xXXXX |
| * The highest 8 bits is Peripheral ID |
| * The lowest 8 bits is Instance ID |
| */ |
| #define IMX_CCM_PERIPHERAL_MASK 0xFF00UL |
| #define IMX_CCM_INSTANCE_MASK 0x00FFUL |
| |
| #define IMX_CCM_CORESYS_CLK 0x0000UL |
| #define IMX_CCM_PLATFORM_CLK 0x0100UL |
| #define IMX_CCM_BUS_CLK 0x0200UL |
| |
| #define IMX_CCM_LPUART_CLK 0x0300UL |
| |
| #define IMX_CCM_LPI2C_CLK 0x0400UL |
| |
| #define IMX_CCM_LPSPI_CLK 0x0500UL |
| |
| #define IMX_CCM_USDHC1_CLK 0x0600UL |
| #define IMX_CCM_USDHC2_CLK 0x0601UL |
| |
| #define IMX_CCM_EDMA_CLK 0x0700UL |
| |
| #define IMX_CCM_UART1_CLK 0x0800UL |
| #define IMX_CCM_UART2_CLK 0x0801UL |
| #define IMX_CCM_UART3_CLK 0x0802UL |
| #define IMX_CCM_UART4_CLK 0x0803UL |
| |
| #define IMX_CCM_CAN_CLK 0x0900UL |
| |
| #define IMX_CCM_GPT_CLK 0x0A00UL |
| |
| #define IMX_CCM_SAI1_CLK 0x0B00UL |
| #define IMX_CCM_SAI2_CLK 0x0B01UL |
| #define IMX_CCM_SAI3_CLK 0x0B02UL |
| |
| #define IMX_CCM_PWM_CLK 0x0C00UL |
| |
| #define IMX_CCM_QTMR_CLK 0x0D00UL |
| |
| #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ */ |
