| # Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com> |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| config SOC_RISCV32_LITEX_VEXRISCV |
| bool "LiteX VexRiscv system implementation" |
| select RISCV |
| select ATOMIC_OPERATIONS_C |
| select INCLUDE_RESET_VECTOR |
| select RISCV_ISA_RV32I |
| select RISCV_ISA_EXT_M |
| select RISCV_ISA_EXT_A |
| select RISCV_ISA_EXT_ZICSR |
| select RISCV_ISA_EXT_ZIFENCEI |
| |
| if SOC_RISCV32_LITEX_VEXRISCV |
| |
| config LITEX_CSR_DATA_WIDTH |
| int "Select Control/Status register width" |
| default 32 |
| |
| endif # SOC_RISCV32_LITEX_VEXRISCV |
