| /* |
| * SPDX-License-Identifier: Apache-2.0 |
| * Copyright (C) 2022, Intel Corporation |
| * Description: |
| * Section of the DTS file containing definitions for the HPS |
| * heavily modified for Zephyr |
| */ |
| |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| aliases { |
| serial0 = &uart0; |
| serial1 = &uart1; |
| eth0 = &gmac0; |
| usb = &usb1; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a9"; |
| device_type = "cpu"; |
| reg = <0>; |
| /* next-level-cache = <&L2>; */ /*cache driver not available yet */ |
| }; |
| cpu1: cpu@1 { |
| compatible = "arm,cortex-a9"; |
| device_type = "cpu"; |
| reg = <1>; |
| /* next-level-cache = <&L2>; */ /*cache driver not available yet */ |
| }; |
| }; |
| |
| intc: intc@fffed000 { |
| compatible = "arm,gic-v1", "arm,gic"; |
| #interrupt-cells = <4>; |
| interrupt-controller; |
| reg = <0xfffed000 0x1000>, |
| <0xfffec100 0x100>; |
| }; |
| |
| soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "simple-bus"; |
| device_type = "soc"; |
| interrupt-parent = <&intc>; |
| ranges; |
| |
| L2: l2-cache@fffef000 { |
| compatible = "arm,pl330-cache"; |
| reg = <0xfffef000 0x1000>; |
| interrupts = <0 38 0x04 IRQ_DEFAULT_PRIORITY>; |
| status= "okay"; |
| }; |
| |
| clkmgr@ffd04000 { |
| compatible = "altr,clk-mgr"; |
| reg = <0xffd04000 0x1000>; |
| clocks { |
| osc1: osc1 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| }; |
| osc2: osc2 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <25000000>; |
| }; |
| f2s_periph_ref_clk: f2s_periph_ref_clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <50000000>; |
| }; |
| f2s_sdram_ref_clk: f2s_sdram_ref_clk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <100000000>; |
| }; |
| }; |
| }; |
| |
| sysmgr: sysmgr@ffd08000 { |
| compatible = "altr,sys-mgr", "syscon"; |
| reg = <0xffd08000 0x4000>; |
| status = "okay"; |
| }; |
| ocram: sram@ffff0000 { |
| compatible = "zephyr,memory-region" , "mmio-sram"; |
| reg = <0xffff0000 0x10000>; |
| zephyr,memory-region = "OCRAM"; |
| }; |
| |
| arch_timer: timer@fffec200 { |
| compatible = "arm,armv8-timer"; |
| status = "okay"; |
| interrupt-names = "irq_0", "irq_1", "irq_2", "irq_3"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_PPI 14 IRQ_TYPE_EDGE |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_PPI 11 IRQ_TYPE_EDGE |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_PPI 10 IRQ_TYPE_EDGE |
| IRQ_DEFAULT_PRIORITY>; |
| reg = <0xfffec200 0x1C>; |
| clocks = <&osc1>; |
| }; |
| |
| uart0: serial0@ffc02000 { |
| compatible = "ns16550","snps,dw-apb-uart"; |
| reg = <0xffc02000 0x1000>; |
| interrupts = <0 162 4 IRQ_DEFAULT_PRIORITY>; |
| reg-shift = <2>; |
| clock-frequency = <100000000>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| uart1: serial1@ffc03000 { |
| compatible = "ns16550","snps,dw-apb-uart"; |
| reg = <0xffc03000 0x1000>; |
| interrupts = <0 163 4 IRQ_DEFAULT_PRIORITY>; |
| reg-shift = <2>; |
| clock-frequency = <100000000>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| gmac0: ethernet@ff700000 { |
| compatible = "snps,ethernet-cyclonev"; |
| reg = <0xff700000 0x2000>; |
| interrupts = <0 115 4 IRQ_DEFAULT_PRIORITY>; |
| emac-index = <0>; |
| status = "disabled"; |
| }; |
| |
| gmac1: ethernet@ff702000 { |
| compatible = "snps,ethernet-cyclonev"; |
| reg = <0xff702000 0x2000>; |
| interrupts = <0 120 4 IRQ_DEFAULT_PRIORITY>; |
| emac-index = <1>; |
| status = "disabled"; |
| }; |
| |
| gpio0: gpio@ff708000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,designware-gpio"; |
| reg = <0xff708000 0x1000>; |
| interrupts = <0 164 4 IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| ngpios = <29>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| gpio1: gpio@ff709000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,designware-gpio"; |
| reg = <0xff709000 0x1000>; |
| interrupts = <0 165 4 IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| ngpios = <29>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| gpio2: gpio@ff70a000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,designware-gpio"; |
| reg = <0xff70a000 0x1000>; |
| interrupts = <0 166 4 IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| ngpios = <27>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| i2c0: i2c@ffc04000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,designware-i2c"; |
| reg = <0xffc04000 0x1000>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupts = <0 158 0x4 IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&intc>; |
| status = "okay"; |
| }; |
| |
| i2c1: i2c@ffc05000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,designware-i2c"; |
| reg = <0xffc05000 0x1000>; |
| interrupts = <0 159 0x4 IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@ffc06000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,designware-i2c"; |
| reg = <0xffc06000 0x1000>; |
| interrupts = <0 160 0x4 IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@ffc07000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "snps,designware-i2c"; |
| reg = <0xffc07000 0x1000>; |
| interrupts = <0 161 0x4 IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| |
| usb0: usb@ffb30000 { |
| compatible = "snps,dwc2"; |
| reg = <0xffb30000 0xffff>; |
| interrupts = <0 127 4 IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&intc>; |
| status = "disabled"; |
| }; |
| |
| usb1: usb@ffb40000 { |
| compatible = "snps,dwc2"; |
| reg = <0xffb40000 0xffff>; |
| interrupts = <0 128 4 IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&intc>; |
| status = "okay"; |
| }; |
| |
| spi0: spi@fff00000 { |
| compatible = "snps,designware-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xfff00000 0x1000>; |
| fifo-depth = <256>; |
| max-xfer-size = <32>; |
| interrupts = <0 154 4 IRQ_DEFAULT_PRIORITY>; |
| clock-frequency = <200000000>; |
| status = "okay"; |
| }; |
| |
| spi1: spi@fff01000 { |
| compatible = "snps,designware-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xfff01000 0x1000>; |
| fifo-depth = <256>; |
| max-xfer-size = <32>; |
| interrupts = <0 155 4 IRQ_DEFAULT_PRIORITY>; |
| clock-frequency = <200000000>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
