| # Copyright (c) 2019 Vestas Wind Systems A/S |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| title: NXP Kinetis SCG (System Clock Generator) |
| |
| description: > |
| This is a representation of the NXP Kinetis SCG IP node |
| |
| compatible: "nxp,kinetis-scg" |
| |
| include: [clock-controller.yaml, base.yaml] |
| |
| properties: |
| reg: |
| required: true |
| |
| label: |
| required: true |
| |
| clk-divider-slow: |
| type: int |
| description: system clock to slow clock divider |
| required: true |
| |
| clk-divider-bus: |
| type: int |
| description: system clock to bus clock divider |
| required: true |
| |
| clk-divider-core: |
| type: int |
| description: system clock to core clock divider |
| required: true |
| |
| clk-source: |
| type: int |
| description: system clock source |
| required: false |
| |
| sosc-freq: |
| type: int |
| description: system oscillator (e.g. xtal) frequency |
| required: false |
| |
| sosc-mode: |
| type: int |
| description: system oscillator mode |
| required: false |
| |
| sosc-divider-1: |
| type: int |
| description: system oscillator divider 1 |
| required: false |
| |
| sosc-divider-2: |
| type: int |
| description: system oscillator divider 2 |
| required: false |
| |
| sirc-range: |
| type: int |
| description: slow internal reference clock range in MHz |
| required: true |
| |
| sirc-divider-1: |
| type: int |
| description: slow internal reference clock divider 1 |
| required: true |
| |
| sirc-divider-2: |
| type: int |
| description: slow internal reference clock divider 2 |
| required: true |
| |
| firc-range: |
| type: int |
| description: fast internal reference clock range in MHz |
| required: true |
| |
| firc-divider-1: |
| type: int |
| description: fast internal reference clock divider 1 |
| required: true |
| |
| firc-divider-2: |
| type: int |
| description: fast internal reference clock divider 2 |
| required: true |
| |
| spll-source: |
| type: int |
| description: system phase-locked loop clock source |
| required: true |
| |
| spll-divider-pre: |
| type: int |
| description: system phase-locked loop reference clock divider |
| required: true |
| |
| spll-multiplier: |
| type: int |
| description: system phase-locked loop reference clock multiplier |
| required: true |
| |
| spll-divider-1: |
| type: int |
| description: system phase-locked loop divider 1 |
| required: true |
| |
| spll-divider-2: |
| type: int |
| description: system phase-locked loop divider 2 |
| required: true |
| |
| clkout-source: |
| type: int |
| description: clockout clock source |
| required: false |
| |
| "#clock-cells": |
| const: 1 |
| |
| clock-cells: |
| - name |