| # |
| # Xilinx AXI 1G / 2.5G Ethernet Subsystem |
| # |
| # Copyright (c) 2024, CISPA Helmholtz Center for Information Security |
| # SPDX-License-Identifier: Apache-2.0 |
| # |
| |
| config ETH_XILINX_AXIENET |
| bool "Xilinx AXI Ethernet Driver" |
| default y |
| depends on DT_HAS_XLNX_AXI_ETHERNET_1_00_A_ENABLED |
| depends on DMA_XILINX_AXI_DMA |
| help |
| Enable Xilinx 1G / 2.5G AXI Ethernet driver, |
| commonly found on FPGAs. |
| |
| config ETH_XILINX_AXIENET_BUFFER_NUM_TX |
| int "Number of buffers for concurrent transmission (TX)." |
| depends on ETH_XILINX_AXIENET |
| default DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_TX |
| range 2 DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_TX |
| help |
| Number of buffers for transmission allocated in the Xilinx AXI Ethernet driver. |
| This limits how many transmissions can be in-flight at the same time. |
| This cannot exceed the number of available TX buffers in the AXI DMA. However, |
| in scenarios with multiple AXI DMAs for different purposes in the system, it |
| may be desirable to reduce the number of concurrent transmissions to conserve |
| resources. |
| |
| config ETH_XILINX_AXIENET_BUFFER_NUM_RX |
| int "Number of buffers for concurrent reception (RX)." |
| depends on ETH_XILINX_AXIENET |
| default DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_RX |
| range 2 DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_RX |
| help |
| Number of buffers for reception allocated in the Xilinx AXI Ethernet driver. |
| This limits how many transmissions can be in-flight at the same time. |
| This cannot exceed the number of available RX buffers in the AXI DMA. However, |
| in scenarios with multiple AXI DMAs for different purposes in the system, it |
| may be desirable to reduce the number of concurrent transmissions to conserve |
| resources. |
