| # Copyright (c) 2024 Nordic Semiconductor ASA |
| # Copyright (c) 2025 Tenstorrent AI ULC |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| config MSPI_DW |
| bool "DesignWare SSI controller driver" |
| default y |
| depends on DT_HAS_SNPS_DESIGNWARE_SSI_ENABLED |
| select PINCTRL if $(dt_compat_any_has_prop,$(DT_COMPAT_SNPS_DESIGNWARE_SSI),pinctrl-0) |
| imply MSPI_XIP |
| imply MSPI_TIMING |
| |
| if MSPI_DW |
| |
| config MSPI_DW_HANDLE_FIFOS_IN_SYSTEM_WORKQUEUE |
| bool "Handle FIFO in system workqueue" |
| help |
| When the driver does not use DMA for transferring data to/from the |
| SSI FIFOs, handling of those may take a significant amount of time. |
| It may be destructive for some applications if that time is spent |
| in the interrupt context. This option allows offloading the job to |
| the system workqueue. |
| |
| config MSPI_DW_TXD_DIV |
| int "Designware SSI TX Drive edge divisor" |
| default 4 |
| help |
| Division factor to apply to calculated BAUDR value when writing it |
| to the TXD_DRIVE_EDGE register in DDR mode. Note that the maximum |
| value of this register is (BAUDR / 2) - 1. |
| |
| config MSPI_DW_TXD_MUL |
| int "Designware SSI TX Drive edge multiplier" |
| default 1 |
| help |
| Multiplication factor to apply to calculated BAUDR value when writing |
| it to the TXD_DRIVE_EDGE register in DDR mode. Note that the maximum |
| value of this register is (BAUDR / 2) - 1. |
| |
| endif # MSPI_DW |
