| /dts-v1/; |
| |
| #include <arm/armv7-m.dtsi> |
| #include "arm/beetle/soc_irq.h" |
| |
| / { |
| compatible = "arm,beetle"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| chosen { |
| zephyr,console = &uart1; |
| zephyr,sram = &sram0; |
| zephyr,flash = &flash0; |
| }; |
| |
| cpus { |
| cpu@0 { |
| compatible = "arm,cortex-m3"; |
| }; |
| }; |
| |
| sram0: memory { |
| compatible = "mmio-sram"; |
| reg = <0x20000000 0x20000>; |
| }; |
| |
| flash0: flash { |
| reg = <0 0x40000>; |
| }; |
| |
| soc { |
| timer0: timer@40000000 { |
| compatible = "arm,cmsdk-timer"; |
| reg = <0x40000000 0x1000>; |
| interrupts = <IRQ_TIMER0 3>; |
| }; |
| |
| timer1: timer@40001000 { |
| compatible = "arm,cmsdk-timer"; |
| reg = <0x40001000 0x1000>; |
| interrupts = <IRQ_TIMER1 3>; |
| }; |
| |
| dtimer0: dtimer@40002000 { |
| compatible = "arm,cmsdk-dtimer"; |
| reg = <0x40000000 0x1000>; |
| interrupts = <IRQ_DUALTIMER 3>; |
| }; |
| |
| uart0: uart@40004000 { |
| compatible = "arm,cmsdk-uart"; |
| reg = <0x40004000 0x1000>; |
| interrupts = <IRQ_UART0 3>; |
| current-speed = <115200>; |
| label = "UART_0"; |
| }; |
| |
| uart1: uart@40005000 { |
| compatible = "arm,cmsdk-uart"; |
| reg = <0x40005000 0x1000>; |
| interrupts = <IRQ_UART1 3>; |
| current-speed = <115200>; |
| label = "UART_1"; |
| }; |
| |
| wdog0: wdog@40008000 { |
| compatible = "arm,cmsdk-watchdog"; |
| reg = <0x40008000 0x1000>; |
| }; |
| |
| gpio0: gpio@40010000 { |
| compatible = "arm,cmsdk-gpio"; |
| reg = <0x40010000 0x1000>; |
| interrupts = <IRQ_PORT0_ALL 3>; |
| }; |
| |
| gpio1: gpio@40011000 { |
| compatible = "arm,cmsdk-gpio"; |
| reg = <0x40011000 0x1000>; |
| interrupts = <IRQ_PORT1_ALL 3>; |
| }; |
| |
| gpio2: gpio@40012000 { |
| compatible = "arm,cmsdk-gpio"; |
| reg = <0x40012000 0x1000>; |
| interrupts = <IRQ_PORT2_ALL 3>; |
| }; |
| |
| gpio3: gpio@40013000 { |
| compatible = "arm,cmsdk-gpio"; |
| reg = <0x40013000 0x1000>; |
| interrupts = <IRQ_PORT3_ALL 3>; |
| }; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <3>; |
| }; |