blob: ff731d07fca1b0de66ff5eabbbcf3696396bf512 [file] [log] [blame]
/*
* Copyright (c) 2021 BrainCo Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/adc/gd32f3x0.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
clock-frequency = <108000000>;
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
soc {
sram0: memory@20000000 {
compatible = "mmio-sram";
};
fmc: flash-controller@40022000 {
compatible = "gd,gd32-flash-controller";
reg = <0x40022000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "soc-nv-flash";
};
};
usart0: usart@40013800 {
compatible = "gd,gd32-usart";
reg = <0x40013800 0x400>;
interrupts = <27 0>;
rcu-periph-clock = <0x060e>;
status = "disabled";
};
usart1: usart@40004400 {
compatible = "gd,gd32-usart";
reg = <0x40004400 0x400>;
interrupts = <28 0>;
rcu-periph-clock = <0x0711>;
status = "disabled";
};
adc0: adc@40012400 {
compatible = "gd,gd32-adc";
reg = <0x40012400 0x400>;
interrupts = <12 0>;
rcu-periph-clock = <0x609>;
rcu-clock-source = <GD32_RCU_ADCCK_APB2_DIV4>;
channels = <16>;
status = "disabled";
#io-channel-cells = <1>;
};
dma0: dma@40020000 {
compatible = "gd,gd32-dma";
reg = <0x40020000 0x400>;
interrupts = <9 0>, <10 0>, <11 0>, <48 0>;
rcu-periph-clock = <0x500>;
dma-channels = <7>;
#dma-cells = <1>;
status = "disabled";
};
pinctrl: pin-controller@48000000 {
compatible = "gd,gd32-pinctrl-af";
reg = <0x48000000 0x1800>;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
gpioa: gpio@48000000 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000000 0x400>;
rcu-periph-clock = <0x511>;
status = "disabled";
};
gpiob: gpio@48000400 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000400 0x400>;
rcu-periph-clock = <0x512>;
status = "disabled";
};
gpioc: gpio@48000800 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000800 0x400>;
rcu-periph-clock = <0x513>;
status = "disabled";
};
gpiod: gpio@48000c00 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000c00 0x400>;
rcu-periph-clock = <0x514>;
status = "disabled";
};
gpiof: gpio@48001400 {
compatible = "gd,gd32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48001400 0x400>;
rcu-periph-clock = <0x516>;
status = "disabled";
};
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};