| /* |
| * Copyright (c) 2018 Intel Corporation |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #ifndef __INC_BOARD_H |
| #define __INC_BOARD_H |
| |
| /* Map APL GPIO pins to pins on UP Squared HAT */ |
| #define UP2_HAT_PIN_3_DEV APL_GPIO_DEV_N_0 |
| #define UP2_HAT_PIN_3 APL_GPIO_28 |
| |
| #define UP2_HAT_PIN_5_DEV APL_GPIO_DEV_N_0 |
| #define UP2_HAT_PIN_5 APL_GPIO_29 |
| |
| #define UP2_HAT_PIN_7_DEV APL_GPIO_DEV_NW_2 |
| #define UP2_HAT_PIN_7 APL_GPIO_123 |
| |
| #define UP2_HAT_PIN_8_DEV APL_GPIO_DEV_N_1 |
| #define UP2_HAT_PIN_8 APL_GPIO_43 |
| |
| #define UP2_HAT_PIN_10_DEV APL_GPIO_DEV_N_1 |
| #define UP2_HAT_PIN_10 APL_GPIO_42 |
| |
| #define UP2_HAT_PIN_11_DEV APL_GPIO_DEV_N_1 |
| #define UP2_HAT_PIN_11 APL_GPIO_44 |
| |
| #define UP2_HAT_PIN_12_DEV APL_GPIO_DEV_W_0 |
| #define UP2_HAT_PIN_12 APL_GPIO_146 |
| |
| #define UP2_HAT_PIN_13_DEV APL_GPIO_DEV_NW_2 |
| #define UP2_HAT_PIN_13 APL_GPIO_122 |
| |
| #define UP2_HAT_PIN_15_DEV APL_GPIO_DEV_NW_2 |
| #define UP2_HAT_PIN_15 APL_GPIO_121 |
| |
| #define UP2_HAT_PIN_16_DEV APL_GPIO_DEV_N_1 |
| #define UP2_HAT_PIN_16 APL_GPIO_37 |
| |
| #define UP2_HAT_PIN_18_DEV APL_GPIO_DEV_NW_1 |
| #define UP2_HAT_PIN_18 APL_GPIO_88 |
| |
| #define UP2_HAT_PIN_19_DEV APL_GPIO_DEV_NW_2 |
| #define UP2_HAT_PIN_19 APL_GPIO_110 |
| |
| #define UP2_HAT_PIN_21_DEV APL_GPIO_DEV_NW_2 |
| #define UP2_HAT_PIN_21 APL_GPIO_109 |
| |
| #define UP2_HAT_PIN_22_DEV APL_GPIO_DEV_NW_1 |
| #define UP2_HAT_PIN_22 APL_GPIO_85 |
| |
| #define UP2_HAT_PIN_23_DEV APL_GPIO_DEV_NW_1 |
| #define UP2_HAT_PIN_23 APL_GPIO_104 |
| |
| #define UP2_HAT_PIN_24_DEV APL_GPIO_DEV_NW_1 |
| #define UP2_HAT_PIN_24 APL_GPIO_105 |
| |
| #define UP2_HAT_PIN_26_DEV APL_GPIO_DEV_NW_1 |
| #define UP2_HAT_PIN_26 APL_GPIO_106 |
| |
| #define UP2_HAT_PIN_27_DEV APL_GPIO_DEV_N_0 |
| #define UP2_HAT_PIN_27 APL_GPIO_30 |
| |
| #define UP2_HAT_PIN_28_DEV APL_GPIO_DEV_N_0 |
| #define UP2_HAT_PIN_28 APL_GPIO_31 |
| |
| #define UP2_HAT_PIN_29_DEV APL_GPIO_DEV_NW_2 |
| #define UP2_HAT_PIN_29 APL_GPIO_120 |
| |
| #define UP2_HAT_PIN_31_DEV APL_GPIO_DEV_NW_1 |
| #define UP2_HAT_PIN_31 APL_GPIO_87 |
| |
| #define UP2_HAT_PIN_32_DEV APL_GPIO_DEV_N_1 |
| #define UP2_HAT_PIN_32 APL_GPIO_34 |
| |
| #define UP2_HAT_PIN_33_DEV APL_GPIO_DEV_N_1 |
| #define UP2_HAT_PIN_33 APL_GPIO_35 |
| |
| #define UP2_HAT_PIN_35_DEV APL_GPIO_DEV_W_0 |
| #define UP2_HAT_PIN_35 APL_GPIO_147 |
| |
| #define UP2_HAT_PIN_36_DEV APL_GPIO_DEV_N_1 |
| #define UP2_HAT_PIN_36 APL_GPIO_45 |
| |
| #define UP2_HAT_PIN_37_DEV APL_GPIO_DEV_NW_1 |
| #define UP2_HAT_PIN_37 APL_GPIO_86 |
| |
| #define UP2_HAT_PIN_38_DEV APL_GPIO_DEV_W_0 |
| #define UP2_HAT_PIN_38 APL_GPIO_148 |
| |
| #define UP2_HAT_PIN_40_DEV APL_GPIO_DEV_W_0 |
| #define UP2_HAT_PIN_40 APL_GPIO_149 |
| |
| #endif /* __INC_BOARD_H */ |
