| /* |
| * Copyright (c) 2022 Intel Corporation |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #ifndef ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_ |
| #define ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_ |
| |
| |
| /* macros related to interrupt handling */ |
| #define XTENSA_IRQ_NUM_SHIFT 0 |
| #define CAVS_IRQ_NUM_SHIFT 8 |
| #define XTENSA_IRQ_NUM_MASK 0xff |
| #define CAVS_IRQ_NUM_MASK 0xff |
| |
| /* |
| * IRQs are mapped on 2 levels. 3rd and 4th level are left as 0x00. |
| * |
| * 1. Peripheral Register bit offset. |
| * 2. CAVS logic bit offset. |
| */ |
| #define XTENSA_IRQ_NUMBER(_irq) \ |
| ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) |
| #define CAVS_IRQ_NUMBER(_irq) \ |
| (((_irq >> CAVS_IRQ_NUM_SHIFT) & CAVS_IRQ_NUM_MASK) - 1) |
| |
| /* Macro that aggregates the bi-level interrupt into an IRQ number */ |
| #define SOC_AGGREGATE_IRQ(cavs_irq, core_irq) \ |
| ( \ |
| ((core_irq & XTENSA_IRQ_NUM_MASK) << XTENSA_IRQ_NUM_SHIFT) | \ |
| (((cavs_irq + 1) & CAVS_IRQ_NUM_MASK) << CAVS_IRQ_NUM_SHIFT) \ |
| ) |
| |
| #define CAVS_L2_AGG_INT_LEVEL2 DT_IRQN(DT_INST(0, intel_cavs_intc)) |
| #define CAVS_L2_AGG_INT_LEVEL3 DT_IRQN(DT_INST(1, intel_cavs_intc)) |
| #define CAVS_L2_AGG_INT_LEVEL4 DT_IRQN(DT_INST(2, intel_cavs_intc)) |
| #define CAVS_L2_AGG_INT_LEVEL5 DT_IRQN(DT_INST(3, intel_cavs_intc)) |
| |
| #define CAVS_ICTL_INT_CPU_OFFSET(x) (0x40 * x) |
| |
| |
| #endif |