| # |
| # Seagate FireCuda Gaming SSD (FaZe) board |
| # |
| |
| # An external debug probe must be connected to the SWD port (4-pins J2 header). |
| # Here we assume that a ST-LINK in-circuit debugger/programmer is used. You may |
| # have to replace it with your own interface here. |
| source [find interface/stlink.cfg] |
| |
| # NXP LPC11U24 Cortex-M0 with 128KB Flash and 20KB + 4KB SRAM |
| set WORKAREASIZE 0x5000 |
| |
| set CPUTAPID 0x0bc11477 |
| |
| source [find target/lpc11xx.cfg] |
| |
| # This ensures that the interrupt vectors (0x0000-0x0200) are re-mapped to |
| # flash after the "reset halt" command. Else the load/verify functions won't |
| # work correctly. |
| # |
| # Table 8. System memory remap register (SYSMEMREMAP, address 0x40048000) bit |
| # description |
| # Bit Symbol Value Description |
| # 1:0 MAP System memory remap |
| # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to |
| # Boot ROM. |
| # 0x1 User RAM Mode. Interrupt vectors are re-mapped to |
| # Static RAM. |
| # 0x2 User Flash Mode. Interrupt vectors are not re-mapped |
| # and reside in Flash. |
| # 31:2 - - Reserved. |
| $_TARGETNAME configure -event reset-end { |
| mww 0x40048000 0x02 |
| } |
| |
| # Enable Zephyr thread awareness. |
| $_TARGETNAME configure -rtos Zephyr |
| |
| adapter_khz 100 |
