dts/bindings/memory-controllers/st,stm32-fmc-sdram.yaml

# Copyright (c) 2020, Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0

description: |
  STM32 Flexible Memory Controller (SDRAM controller).

  The FMC SDRAM controller can be used to interface with external SDRAM
  memories. Up to 2 SDRAM banks are supported with independent configuration. It
  is worth to note that while settings are independent, some are shared or are
  required to be set according to the most constraining device. Refer to the
  properties description or the datasheet for more details.

  The FMC SDRAM controller is defined below the FMC node and SDRAM banks are
  defined as child nodes of the FMC SDRAM node. You can either have bank 1 (@0),
  bank 2 (@1) or both. You can enable the FMC SDRAM controller in your board
  DeviceTree file like this:

  &fmc {
      status = "okay";
      pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;

      sdram {
          status = "okay";

          power-up-delay = <100>;
          num-auto-refresh = <8>;
          mode-register = <0x220>;
          refresh-rate = <603>;

          bank@0 {
              reg = <0>;

              st,sdram-control = <STM32_FMC_SDRAM_NC_9
                                  STM32_FMC_SDRAM_NR_12
                                  STM32_FMC_SDRAM_MWID_32
                                  STM32_FMC_SDRAM_NB_4
                                  STM32_FMC_SDRAM_CAS_2
                                  STM32_FMC_SDRAM_SDCLK_PERIOD_2
                                  STM32_FMC_SDRAM_RBURST_ENABLE
                                  STM32_FMC_SDRAM_RPIPE_0>;
              st,sdram-timing = <2 6 4 6 2 2 2>;
          };

          bank@1 {
              reg = <1>;
              ...
          };
      };
  };

  Note that you will find definitions for the st,sdram-control field at
  dt-bindings/memory-controller/stm32-fmc-sdram.h. This file is already included
  in the SoC DeviceTree files.

  Finally, in order to make the memory available you will need to define new
  memory device/s in DeviceTree:

  sdram1: sdram@c0000000 {
      device_type = "memory";
      reg = <0xc000000 DT_SIZE_M(X)>;
  };

  sdram2: sdram@d0000000 {
      device_type = "memory";
      reg = <0xd000000 DT_SIZE_M(X)>;
  };

  It is important to use sdram1 and sdram2 node labels for bank 1 and bank 2
  respectively. Memory addresses are 0xc0000000 and 0xd0000000 for bank 1 and
  bank 2 respectively.

compatible: "st,stm32-fmc-sdram"

include: base.yaml

properties:
  label:
    required: true

  "#address-cells":
    required: true
    const: 1

  "#size-cells":
    required: true
    const: 0

  power-up-delay:
    type: int
    default: 100
    description: Power-up delay in microseconds.

  num-auto-refresh:
    type: int
    default: 8
    description: Number of auto-refresh commands issued.

  mode-register:
    type: int
    required: true
    description:
      A 14-bit field that defines the SDRAM Mode Register content. The mode
      register bits are also used to program the extended mode register for
      mobile SDRAM.

  refresh-rate:
    type: int
    required: true
    description:
      A 13-bit field defines the refresh rate of the SDRAM device. It is
      expressed in number of memory clock cycles. It must be set at least to
      41 SDRAM clock cycles.

child-binding:
  description: SDRAM bank.

  properties:
    reg:
      type: int
      required: true

    st,sdram-control:
      type: array
      required: true
      description: |
        SDRAM control configuration. Expected fields, in order, are,

        - NC: Number of bits of a column address.
        - NR: Number of bits of a row address.
        - MWID: Memory device width.
        - NB: Number of internal banks.
        - CAS: SDRAM CAS latency in number of memory clock cycles.
        - SDCLK: SDRAM clock period. If two SDRAM devices are used both should
          have the same value.
        - RBURST: Enable burst read mode. If two SDRAM devices are used both
          should have the same value.
        - RPIPE: Delay, in fmc_ker_ck clock cycles, for reading data after CAS
          latency. If two SDRAM devices are used both should have the same
          value.

    st,sdram-timing:
      type: array
      required: true
      description: |
        SDRAM timing configuration. Expected fields, in order, are,

        - TMRD: Delay between a Load Mode Register command and an Active or
          Refresh command in number of memory clock cycles.
        - TXSR: Delay from releasing the Self-refresh command to issuing the
          Activate command in number of memory clock cycles. If two SDRAM
          devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with
          the same TXSR timing corresponding to the slowest SDRAM device
        - TRAS: Minimum Self-refresh period in number of memory clock cycles.
        - TRC: Delay between the Refresh command and the Activate command, as
          well as the delay between two consecutive Refresh commands. It is
          expressed in number of memory clock cycles. If two SDRAM devices are
          used, the TRC must be programmed with the timings of the slowest
          device in both banks.
        - TWP: Delay between a Write and a Precharge command in number of memory
          clock cycles
        - TRP: Delay between a Precharge command and another command in number
          of memory clock cycles. If two SDRAM devices are used, the TRP must be
          programmed with the timing of the slowest device in both banks.
        - TRCD: Delay between the Activate command and a Read/Write command in
          number of memory clock cycles.