dts/bindings/fpga/lattice,ice40-fpga-base.yaml

# Copyright (c) 2022 Meta
# SPDX-License-Identifier: Apache-2.0

description: Lattice iCE40 FPGA base

compatible: "lattice,ice40-fpga-base"

include: spi-device.yaml

properties:
  cdone-gpios:
    type: phandle-array
    required: true
    description: |
      Configuration Done output from iCE40.
      Example usage:
      cdone-gpios = <&gpio0 0 0>;
  creset-gpios:
    type: phandle-array
    required: true
    description: |
      Configuration Reset input on iCE40.
      Example usage:
      creset-gpios = <&gpio0 1 GPIO_PUSH_PULL);
  creset-delay-us:
    type: int
    default: 1
    description: |
      Delay (in microseconds) between asserting CRESET_B and releasing CRESET_B.
      The datasheet specifies a minimum of 200ns, therefore the default is set
      to 1us.
  config-delay-us:
    type: int
    default: 1200
    description: |
      Delay (in microseconds) after releasing CRESET_B to clear internal configuration memory.
      The datasheet specifies a minimum of 1200us, which is the default.
  leading-clocks:
    type: int
    default: 8
    description: |
      Prior to sending the bitstream, issue this number of leading clocks with SPI_CS pulled high.
      The datasheet specifies 8 dummy cycles, which is the default.
  trailing-clocks:
    type: int
    default: 49
    description: |
      After sending the bitstream, issue this number of trailing clocks with SPI_CS pulled high.
      The datasheet specifies 49 dummy cycles, which is the default.